52665 Commits

Author SHA1 Message Date
Helena Kotas
b42fa8645c
[DXIL] Add lowering for ceil (#87043)
Add lowering of llvm.ceil intrinsics to DXIL ops.

Fixes #86984
2024-03-29 15:09:44 -04:00
Alex MacLean
7daa65a088
Reland "[NVPTX] Use .common linkage for common globals" (#86824)
Switch from `.weak` to `.common` linkage for common global variables
where possible. The `.common` linkage is described in
[PTX ISA 11.6.4. Linking Directives: .common]
(https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#linking-directives-common)
> Declares identifier to be globally visible but “common”.
>
>Common symbols are similar to globally visible symbols. However
multiple object files may declare the same common symbol and they may
have different types and sizes and references to a symbol get resolved
against a common symbol with the largest size.
>
>Only one object file can initialize a common symbol and that must have
the largest size among all other definitions of that common symbol from
different object files.
>
>.common linking directive can be used only on variables with .global
storage. It cannot be used on function symbols or on symbols with opaque
type.

I've updated the logic and tests to only use `.common` for PTX 5.0 or
greater and verified that the new tests now pass with `ptxas`.
2024-03-29 11:58:41 -07:00
Farzon Lotfi
e74332a266
[HLSL][DXIL] HLSL's round should follow roundeven behavior (#87078)
fixes #86999
2024-03-29 13:19:28 -04:00
Shilei Tian
661bb9daae
[GlobalISel] Handle div-by-pow2 (#83155)
This patch adds similar handling of div-by-pow2 as in `SelectionDAG`.
2024-03-29 12:41:47 -04:00
Marc Auberer
d3bc9cc99b
[AArch64][GISEL] Regenerate select tests with inline register classes (#87013)
Use inline register class syntax for select test file.
2024-03-29 15:45:06 +01:00
Luke Lau
3f69d90351
[RISCV] Add missing RISCVMaskedPseudo for TIED pseudos (#86787)
This was preventing us from folding away the vmerge into its mask.
2024-03-29 22:21:22 +08:00
Thorsten Schütt
84299df301
[GlobalIsel] add trunc flags (#87045)
https://github.com/llvm/llvm-project/pull/85592
2024-03-29 13:38:08 +01:00
Luke Lau
76ba3c8e64 [RISCV] Add test case for vmerge fold for tied pseudos with rounding mode. NFC 2024-03-29 19:47:09 +08:00
Luke Lau
2a315d800b
[RISCV] Combine (or disjoint ext, ext) -> vwadd (#86929)
DAGCombiner (or InstCombine) will convert an add to an or if the bits
are disjoint, which can prevent what was originally an (add {s,z}ext,
{s,z}ext) from being selected as a vwadd.

This teaches combineBinOp_VLToVWBinOp_VL to recover it by treating it as
an add.
2024-03-29 19:45:24 +08:00
Luke Lau
131be5de90 [RISCV] Add more disjoint or tests for vwadd[u].{w,v}v. NFC 2024-03-29 19:11:26 +08:00
Wang Pengcheng
610b9e23c5
[SDAG] Use shifts if ISD::MUL is illegal when lowering ISD::CTPOP (#86505)
We can avoid libcalls.

Fixes #86205
2024-03-29 15:38:39 +08:00
Sudharsan Veeravalli
e005a09df5
[RISCV][TypePromotion] Dont generate truncs if PromotedType is greater than Source Type (#86941)
We currently check if the source and promoted types are not equal before
generating truncate instructions. This does not work for RV64 where the
promoted type is i64 and this lead to a crash due to the generation of
truncate instructions from i32 to i64.

Fixes #86400
2024-03-28 21:22:05 -07:00
Philip Reames
9ea0396f16
[RISCV] Extend pattern matches involving shNadd to support disjoint or (#87001)
I tried to add representative tests while not duplicating complete
coverage.  If there's other tests you'd like to see, let me know.
2024-03-28 16:34:04 -07:00
Marc Auberer
c482fad2c1
[AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#86972)
Fixes #86917

`FCMP_TRUE` and `FCMP_FALSE` were previously not considered and we ended
up in an llvm_unreachable assertion.
2024-03-28 23:08:38 +01:00
Luke Lau
a3c2d8c072
[RISCV] Combine ({s,u}{div,rem} (zext, zext)) -> (zext ({s,u}{div,rem} (zext, zext))) (#86779)
This narrows unsigned and signed div and rem nodes via
combineBinOpOfZExt.

Unlike other binary ops, there are no widening div or rem instructions.
So we will end up with an extra vzext.vf2.

However I'm assuming that div/rem are expensive enough that by reducing
their EMUL we will gain back the cost.

Alive2 proof: https://alive2.llvm.org/ce/z/Et_L6y
2024-03-29 05:55:38 +08:00
Craig Topper
23d45e55ed
[MCP] Remove dead copies from basic blocks with successors. (#86973)
Previously we wouldn't remove dead copies from basic blocks with
successors. The comment said we didn't want to trust the live-in lists.
The comment is very old so I'm not sure if that's still a concern today.

This patch checks the live-in lists and removes copies from
MaybeDeadCopies if they are referenced by any live-ins in any
successors. We only do this if the tracksLiveness property is set. If
that property is not set, we retain the old behavior.
2024-03-28 14:43:49 -07:00
Helena Kotas
62d6beba97
[DXIL] Add lowering for reversebits and trunc (#86909)
Add lowering of `llvm.bitreverse` and `llvm.trunc` intrinsics to DXIL
ops.

Fixes #86582
Fixes #86581
2024-03-28 17:41:33 -04:00
Zaara Syeda
6582509daa
[AIX] Handle toc-data offset overflowing 16-bits (#80092)
When the toc-data offset overflows the 16-bits, we can truncate the
value to the 16-bit value as the linker will handle overflow through
fixup code.
2024-03-28 13:55:13 -04:00
Jonas Paulsson
16b7cc69ef
[SystemZ] Eliminate call sequence instructions early. (#77812)
On SystemZ, the outgoing argument area which is big enough for all calls
in the function is created once during the prolog, as opposed to
adjusting the stack around each call. The call-sequence instructions are
therefore not really useful any more than to compute the maximum call
frame size, which has so far been done by PEI, but can just as well be
done at an earlier point.

This patch removes the mapping of the CallFrameSetupOpcode and
CallFrameDestroyOpcode and instead computes the MaxCallFrameSize
directly after instruction selection and then removes the ADJCALLSTACK
pseudos. This removes the confusing pseudos and also avoids the problem
of having to keep the call frame size accurate when creating new MBBs.

This fixes #76618 which exposed the need to maintain the call frame size
when splitting blocks (which was not done).
2024-03-28 18:26:38 +01:00
Farzon Lotfi
36b86438d7
[DXIL] Implement pow lowering (#86733)
closes #86179
- `DXILIntrinsicExpansion.cpp` - add the pow expansion to
exp2(y*log2(x))
2024-03-28 12:32:28 -04:00
Craig Topper
f90813543b
[MCP] Use MachineInstr::all_defs instead of MachineInstr::defs in hasOverlappingMultipleDef. (#86889)
defs does not return the defs for inline assembly. We need to use
all_defs to find them.

Fixes #86880.
2024-03-28 08:37:19 -07:00
Amy Kwan
a3efc53f16
[AIX][TLS] Produce a faster local-exec access sequence for the "aix-small-tls" global variable attribute (#83053)
Similar to 3f46e5453d9310b15d974e876f6132e3cf50c4b1, this patch allows
the backend to produce a faster access sequence for the local-exec TLS
model, where loading from the TOC can be avoided, for local-exec TLS
variables that are annotated with the "aix-small-tls" attribute.

The expectation is for local-exec TLS variables to be set with this
attribute through PGO. Furthermore, the optimized access sequence is
only generated for local-exec TLS variables annotated with
"aix-small-tls", only if they are less than ~32KB in size.
2024-03-28 09:18:45 -04:00
Freddy Ye
36b4b9d988
[X86] Support immediate folding for CCMP/CTEST (#86616)
E.g.
%0:gr32 = MOV32ri 81
CTEST32rr %0, %1, 2, 10, implicit-def $eflags, implicit $eflags
=>
CTEST32ri %1, 81, 2, 10, implicit-def $eflags, implicit $eflags
2024-03-28 18:54:32 +08:00
bvlgah
e640d9e725
[RISCV][GlobalISel] Fix legalizing ‘llvm.va_copy’ intrinsic (#86863)
Hi, I spotted a problem when running benchmarking programs on a RISCV64
device.

## Issue

Segmentation faults only occurred while running the programs compiled
with `GlobalISel` enabled.

Here is a small but complete example (it is adopted from [Google's
benchmark
framework](95a9f0d0b4/MicroBenchmarks/libs/benchmark/src/colorprint.cc (L85-L119))
to reproduce the issue,

```cpp
#include <cstdarg>
#include <cstdio>
#include <iostream>
#include <memory>
#include <string>

std::string FormatString(const char* msg, va_list args) {
  // we might need a second shot at this, so pre-emptivly make a copy
  va_list args_cp;
  va_copy(args_cp, args);

  std::size_t size = 256;
  char local_buff[256];
  auto ret = vsnprintf(local_buff, size, msg, args_cp);

  va_end(args_cp);

  // currently there is no error handling for failure, so this is hack.
  // BM_CHECK(ret >= 0);

  if (ret == 0)  // handle empty expansion
    return {};
  else if (static_cast<size_t>(ret) < size)
    return local_buff;
  else {
    // we did not provide a long enough buffer on our first attempt.
    size = static_cast<size_t>(ret) + 1;  // + 1 for the null byte
    std::unique_ptr<char[]> buff(new char[size]);
    ret = vsnprintf(buff.get(), size, msg, args);
    // BM_CHECK(ret > 0 && (static_cast<size_t>(ret)) < size);
    return buff.get();
  }
}

std::string FormatString(const char* msg, ...) {
  va_list args;
  va_start(args, msg);
  auto tmp = FormatString(msg, args);
  va_end(args);
  return tmp;
}

int main() {
  std::string Str =
      FormatString("%-*s %13s %15s %12s", static_cast<int>(20),
                   "Benchmark", "Time", "CPU", "Iterations");
  std::cout << Str << std::endl;
}
```

Use `clang++ -fglobal-isel -o main main.cpp` to compile it.

## Cause

I have examined MIR, it shows that these segmentation faults resulted
from a small mistake about legalizing the intrinsic function
`llvm.va_copy`.


36e74cfdbd/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (L451-L453)

`DstLst` and `Tmp` are placed in the wrong order.

## Changes

I have tweaked the test case `CodeGen/RISCV/GlobalISel/vararg.ll` so
that `s0` is used as the frame pointer (not in all checks) which points
to the starting address of the save area. I believe that it helps reason
about how `llvm.va_copy` is handled.
2024-03-28 13:09:18 +03:00
Luke Lau
eff4593a64 [RISCV] Add test case for missed vwaddu.vv due to add->or combine. NFC
We should be able to recover this with combineBinOp_VLToVWBinOp_VL if we
check that the or has the disjoint flag set.
2024-03-28 16:58:52 +08:00
Vyacheslav Levytskyy
b7ac8fddb5
[SPIR-V] Improve type inference: deduce types of composite data structures (#86782)
This PR improves type inference in general and deduces types of
composite data structures in particular. Also added a way to insert a
bitcast to make a fun call valid in case of arguments types mismatch due
to opaque pointers type inference.

The attached test `pointers/nested-struct-opaque-pointers.ll`
demonstrates new capabilities: the SPIRV code emitted for this test is
now (1) valid in a sense of data field types and (2) accepted by
`spirv-val`.

More strict LIT checks, support of more composite data structures and
improvement of fun calls from the perspective of type correctness are
main todo's at the moment.
2024-03-28 08:08:06 +01:00
Heejin Ahn
6b7ecc7979 Revert "[WebAssembly] Remove threwValue comparison after __wasm_setjmp_test (#86633)"
This reverts commit 52431fdb1ab8d29be078edd55250e06381e4b6b0.

The PR assumed `__threwValue` couldn't be 0, but it could be when the
thrown thing is not a longjmp but an exception, so that `if` check was
actually necessary.
2024-03-28 04:41:29 +00:00
Eli Friedman
036e7ee9d1 [NFC][AArch64] Regenerate regression tests. 2024-03-27 17:08:02 -07:00
Philip Reames
8881281902 [RISCV] Add test coverage for (add (shl Z, c1), Y, (shl Z, c2)) variants
Basically, testing for interaction of shNadd matching with one step
of reassociation in the add.
2024-03-27 14:47:45 -07:00
Shilei Tian
0a43ca731b
[AMDGPU] Fix missing IsExact flag when expanding vector binary operator (#86712) 2024-03-27 17:40:58 -04:00
Florian Hahn
b9cd48f96a
Revert "[TBAA] Add verifier for tbaa.struct metadata (#86709)"
This reverts commit df75183d70e029352a49c93f275db703c81a65c1.

Revert for now as this appears to cause failures on some buildbots,
e.g.:
https://lab.llvm.org/buildbot/#/builders/93/builds/19428/steps/10/logs/stdio
2024-03-27 21:22:15 +00:00
Craig Topper
acab142751 [LegalizeDAG] Freeze index when converting insert_elt/insert_subvector to load/store on stack.
We try clamp the index to be within the bounds of the stack object
we create, but if we don't freeze it, poison can propagate into the
clamp code. This can cause the access to leave the bounds of the
stack object.

We have other instances of this issue in type legalization and extract_elt/subvector,
but posting this patch first for direction check.

Fixes #86717
2024-03-27 13:01:23 -07:00
Craig Topper
0d7ea50d20 [AArch64] Pre-commit test for #86717. NFC 2024-03-27 13:01:23 -07:00
David Green
36e74cfdbd
[AArch64] Clear kill flags when removing FMOVDr. (#86308)
The uses of OldDef/NewDef may not be killed in the same place they
previously were after they are replaced, and so need to be cleared.
2024-03-27 18:36:02 +00:00
Heejin Ahn
52431fdb1a
[WebAssembly] Remove threwValue comparison after __wasm_setjmp_test (#86633)
Currently the code thinks a `longjmp` occurred if both `__THREW__` and
`__threwValue` are nonzero. But `__threwValue` can be 0, and the
`longjmp` library function should change it to 1 in case it is 0:
https://en.cppreference.com/w/c/program/longjmp

Emscripten libraries were not consistent about that, but after
https://github.com/emscripten-core/emscripten/pull/21493 and
https://github.com/emscripten-core/emscripten/pull/21502, we correctly
pass 1 in case the input is 0. So there will be no case `__threwValue`
is 0. And regardless of what `longjmp` library function does, treating
`longjmp`'s 0 input to its second argument as "not longjmping" doesn't
seem right.

I'm not sure where that `__threwValue` checking came from, but probably
I was porting then fastcomp's implementation and moved this part just
verbatim:
9bdc7bb4fc/lib/Target/JSBackend/CallHandlers.h (L274-L278)

Just for the context, how this was discovered:
https://github.com/emscripten-core/emscripten/pull/21502#pullrequestreview-1942160300
2024-03-27 11:11:16 -07:00
Simon Pilgrim
5d3ef06509 [X86] combine-pavg.ll - add demandedelts test coverage for #86284 2024-03-27 17:15:48 +00:00
Simon Pilgrim
dcd0f2b610 [X86] combineExtractFromVectorLoad support extraction from vector of different types to the extraction type/index
combineExtractFromVectorLoad no longer uses the vector we're extracting from to determine the pointer offset calculation, allowing us to extract from types that have been bitcast to work with specific target shuffles.

Fixes #85419
2024-03-27 17:01:41 +00:00
Simon Pilgrim
f92fa7e2cf [X86] Add -verify-machineinstrs to huge stack tests
Help identify EXPENSIVE_CHECKS regressions identified in #84114
2024-03-27 16:26:10 +00:00
Simon Pilgrim
78f0871bee Revert rG58de1e2c5eee548a9b365e3b1554d87317072ad9 "Fix stack layout for frames larger than 2gb (#84114)"
This is failing on some EXPENSIVE_CHECKS buildbots
2024-03-27 16:16:15 +00:00
David Green
313bf28f98
[ARM][MVE] Remove kill flags when reusing VPR register. (#86300)
The vpr register may no longer be killed where it was, so we should be
removing the kill flags.
2024-03-27 16:04:48 +00:00
Wesley Wiser
58de1e2c5e
Fix stack layout for frames larger than 2gb (#84114)
For very large stack frames, the offset from the stack pointer to a local can be more than 2^31 which overflows various `int` offsets in the frame lowering code.

This patch updates the frame lowering code to calculate the offsets as 64-bit values and resolves the overflows, resulting in the correct codegen for very large frames.

Fixes #48911
2024-03-27 15:05:58 +00:00
Brandon Wu
91896607ff
[RISCV] RISCV vector calling convention (1/2) (#77560)
[RISCV] RISCV vector calling convention (1/2)

    This is the vector calling convention based on
    https://github.com/riscv-non-isa/riscv-elf-psabi-doc,
    the idea is to split between "scalar" callee-saved registers
    and "vector" callee-saved registers. "scalar" ones remain the
    original strategy, however, "vector" ones are handled together
    with RVV objects.

    The stack layout would be:

      |--------------------------| <-- FP
      | callee-allocated save    |
      | area for register varargs|
      |--------------------------|
      | callee-saved registers   | <-- scalar callee-saved
      |        (scalar)          |
      |--------------------------|
      | RVV alignment padding    |
      |--------------------------|
      | callee-saved registers   | <-- vector callee-saved
      |        (vector)          |
      |--------------------------|
      | RVV objects              |
      |--------------------------|
      | padding before RVV       |
      |--------------------------|
      | scalar local variables   |
      |--------------------------| <-- BP
      | variable size objects    |
      |--------------------------| <-- SP

    Note: This patch doesn't contain "tuple" type, e.g. vint32m1x2.
          It will be handled in https://github.com/riscv-non-isa/riscv-elf-psabi-doc (2/2).

    Differential Revision: https://reviews.llvm.org/D154576
2024-03-27 23:03:13 +08:00
Simon Pilgrim
6d3ec56d3c [X86] combineExtractWithShuffle - use combineExtractFromVectorLoad to extract scalar load from shuffled vector load
Improves #85419
2024-03-27 14:54:25 +00:00
Kevin P. Neal
f5296df97c
[FPEnv][AMDGPU] Correct AMDGPUSimplifyLibCalls handling of strictfp attribute. (#86705)
The AMDGPUSimplifyLibCalls pass was lowering function calls with the
strictfp attribute to sequences that included function calls incorrectly
lacking the attribute. This patch corrects that.

The pass now also emits the correct constrained fp call instead of
normal FP instructions when in a function with the strictfp attribute.
Replacing non-constrained calls with constrained calls when required
is still on the IRBuilder's TODO list.
2024-03-27 10:20:00 -04:00
Justin Cady
26464f2662
[FreeBSD] Mark __stack_chk_guard dso_local except for PPC64 (#86665)
Adjust logic of 1cb9f37a17ab to match freebsd/freebsd-src@9a4d48a645.

D113443 is the original attempt to bring this FreeBSD patch to
llvm-project,
but it never landed. This change is required to build FreeBSD kernel
modules
with -fstack-protector using a standard LLVM toolchain. The FreeBSD
kernel
loader does not handle R_X86_64_REX_GOTPCRELX relocations.

Fixes #50932.
2024-03-27 09:03:46 -04:00
Simon Pilgrim
e82765bf07 [X86] masked_store.ll - add nounwind to remove cfi noise 2024-03-27 12:22:31 +00:00
Matt Arsenault
ef316da4a2 AMDGPU: Fix dead check prefixes in test 2024-03-27 14:42:47 +03:00
Luke Lau
f15b7deeaa [RISCV] Add test case to show missing vmerge fold on tied pseudos. NFC
Note we can't use vwaddu.wv because it will get combined away with #78403
2024-03-27 17:42:45 +08:00
Julian Nagele
df75183d70
[TBAA] Add verifier for tbaa.struct metadata (#86709)
Adds logic to the IR verifier that checks whether !tbaa.struct nodes are
well-formed. That is, it checks that the operands of !tbaa.struct nodes
are in groups of three, that each group of three operands consists of
two integers and a valid tbaa node, and that the regions described by
the offset and size operands are non-overlapping.

PR: https://github.com/llvm/llvm-project/pull/86709
2024-03-27 10:30:27 +01:00
Luke Lau
6d13263d4a
[RISCV] Add tests for combineBinOpOfZExts. NFC (#86689)
Unlike add, sub and mul, we don't have widening instructions for div,
rem and logical ops, so we don't have any test coverage if we were to
extend combineBinOpOfZExts to handle them.

Adding tests coincidentally revealed that logical ops are already
narrowed as a generic DAG combine via
DAGCombiner::hoistLogicOpWithSameOpcodeHands. So we don't actually need
to run combineBinOpOfZExts on them.
2024-03-27 15:23:34 +08:00