23432 Commits

Author SHA1 Message Date
Charitha Saumya
da608271ae
Revert "[MLIR][Conversion] Add convert-xevm-to-llvm pass." (#148081)
Reverts llvm/llvm-project#147375
2025-07-10 16:21:11 -07:00
Sang Ik Lee
76eead1bd7
[MLIR][Conversion] Add convert-xevm-to-llvm pass. (#147375)
Although XeVM is an LLVM extension dialect,
SPIR-V backend relies on [function
calls](https://llvm.org/docs/SPIRVUsage.html#instructions-as-function-calls)
instead of defining LLVM intrinsics to represent SPIR-V instructions.
convert-xevm-to-llvm pass lowers xevm ops to function declarations and
calls using the above naming convention.
In the future, most part of the pass should be replaced with llvmBuilder
and handled as part of translation to LLVM instead.

---------
Co-authored-by: Artem Kroviakov <artem.kroviakov@intel.com>
2025-07-10 16:04:36 -07:00
Razvan Lupusoru
4859b92b7f
[flang][acc] Update FIR ref, heap, and pointer to be MappableType (#147834)
The MappableType OpenACC type interface is a richer interface that
allows OpenACC dialect to be capable to better interact with a source
dialect, FIR in this case. fir.box and fir.class types already
implemented this interface. Now the same is being done with the other
FIR types that represent variables.

One additional notable change is that fir.array no longer implements
this interface. This is because MappableType is primarily intended for
variables - and FIR variables of this type have storage associated and
thus there's a pointer-like type (fir.ref/heap/pointer) that holds the
array type.

The end goal of promoting these FIR types to MappableType is that we
will soon implement ability to generate recipes outside of the frontend
via this interface.
2025-07-10 15:23:57 -07:00
Sang Ik Lee
61004b7eb5
[MLIR][GPU] Add xevm-attach-target transform pass. (#147372)
Add xevm-attach-target transform pass and unit-tests.

Co-authored-by: by Sang Ik Lee sang.ik.lee@intel.com.
Co-authored-by: Artem Kroviakov artem.kroviakov@intel.com
2025-07-10 15:44:26 -05:00
Adam Siemieniuk
8ad384ba7f
[mlir][xevm] Fix dialect descriptions formatting (#147729)
Fixes markdown formatting of xevm dialect docs.
2025-07-10 19:36:58 +02:00
Ivan Butygin
f60cc63e8c
[mlir][rocdl] Add s.sleep intrinsic (#147936) 2025-07-10 19:27:02 +03:00
Peiming Liu
77d04ffd6d
[mlir][OpenMP] fix compilation warning (#147987) 2025-07-10 08:50:19 -07:00
Kunwar Grover
f96492221d
[mlir][AMDGPU] Add better load/store lowering for full mask (#146748)
This patch adds a better maskedload/maskedstore lowering on amdgpu
backend for loads which are either fully masked or fully unmasked. For
these cases, we can either generate a oob buffer load with no if
condition, or we can generate a normal load with a if condition (if no
fat_raw_buffer space).
2025-07-10 16:11:19 +01:00
Kazu Hirata
86320e0a8f [mlir] Fix warnings
This patch fixes:

  mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp:3047:16: error: unused
  variable 'ctx' [-Werror,-Wunused-variable]

  mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp:3171:16: error: unused
  variable 'ctx' [-Werror,-Wunused-variable]
2025-07-10 07:58:52 -07:00
Kunwar Grover
0227aef688
[mlir][Vector] Add canonicalization for extract_strided_slice(create_mask) (#146745)
extract_strided_slice(create_mask) can be folded into create_mask by
simply subtracting the offsets from the bounds.
2025-07-10 15:43:20 +01:00
Niklas Degener
5954e9c1a5
[MLIR][Target/Cpp] Fix variable naming conflict for function declarations (#147927)
This is a fix for https://github.com/llvm/llvm-project/pull/136102. It
missed scoping for `DeclareFuncOps`.
In scenarios with multiple function declarations, the `valueMapper`
wasn't updated and later uses of values in other functions still used
the assigned names in prior functions.

This is visible in the reproducer here
https://github.com/iree-org/iree/issues/21303: Although the counter for
variable enumeration was reset, as it is visible for the local vars, the
function arguments were mapped to old names. Due to this mapping, the
counter was never increased, and the local variables conflicted with the
arguments.

This fix adds proper scoping for declarations and a test-case to cover
the scenario with multiple `DeclareFuncOps`.
2025-07-10 16:09:49 +02:00
Michael Kruse
628c735010
[MLIR][OpenMP] Add canonical loop operations (#147061)
Add the supporting OpenMP Dialect operations, types, and interfaces for
modelling

MLIR Operations:
 * omp.newcli
 * omp.canonical_loop

MLIR Types:
 * !omp.cli

MLIR Interfaces:
 * LoopTransformationInterface

As a first loop transformations to be able to use these new operation in
follow-up PRs (#144785)
 * omp.unroll_heuristic
2025-07-10 12:53:07 +02:00
Chao Chen
75524dee18
[mlir][xegpu] Relax rank restriction of TensorDescType (#145916) 2025-07-09 19:40:24 -05:00
Kazu Hirata
cd65f8bf17 [mlir] Fix a warning
This patch fixes:

  mlir/lib/Dialect/Vector/Transforms/LowerVectorToFromElementsToShuffleTree.cpp:42:20:
  error: unused variable 'kIndScale' [-Werror,-Wunused-const-variable]
2025-07-09 16:45:18 -07:00
Diego Caballero
ddf9b91f9f
[mlir][Vector] Add vector.shuffle tree transformation (#145740)
This PR adds a new transformation that turns sequences of `vector.to_elements` and `vector.from_elements` into a binary tree of `vector.shuffle` operations.

(Related RFC:
https://discourse.llvm.org/t/rfc-adding-vector-to-elements-op-to-the-vector-dialect/86779).

Example:

```
  %0:4 = vector.to_elements %a : vector<4xf32>
  %1:4 = vector.to_elements %b : vector<4xf32>
  %2:4 = vector.to_elements %c : vector<4xf32>
  %3 = vector.from_elements %0#0, %0#1, %0#2, %0#3,
                            %1#0, %1#1, %1#2, %1#3,
                            %2#0, %2#1, %2#2, %2#3 : vector<12xf32>

==>

  %0 = vector.shuffle %a, %b [0, 1, 2, 3, 4, 5, 6, 7] : vector<4xf32>, vector<4xf32>
  %1 = vector.shuffle %c, %c [0, 1, 2, 3, -1, -1, -1, -1] : vector<4xf32>, vector<4xf32>
  %2 = vector.shuffle %0, %1 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] : vector<8xf32>, vector<8xf32>
```

The algorithm leverages the structured extraction/insertion information
of `vector.to_elements` and `vector.from_elements` operations and builds
a set of intervals to determine the vector length that should be used at
each level of the tree to combine the level inputs in pairs.

There are a few improvements that can be implemented in the future, such
as shuffle mask compression to avoid unnecessarily large vector lengths
with poison values, but I decided to keep things "simpler" and spend
more time documenting the different steps of the algorithm so that
people can follow along.
2025-07-09 16:09:53 -07:00
Adam Siemieniuk
06ae0c2a10
[mlir][xegpu] Remove vector contract to dpas size restriction (#147470)
Removes contraction shape check to allow representing large
workgroup-level workloads in preparation for distribution.
2025-07-09 22:37:06 +02:00
Razvan Lupusoru
8f8b1b0402
[mlir][acc][nfc] Update type interface descriptions (#147807)
PointerLikeType and MappableType interfaces are now described with more
detail.
2025-07-09 12:30:57 -07:00
Diego Caballero
889ac879ce
[mlir][Vector] Remove usage of vector.insertelement/extractelement from Vector (#144413)
This PR is part of the last step to remove `vector.extractelement` and `vector.insertelement` ops.
RFC: https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops

It removes instances of `vector.extractelement` and `vector.insertelement` from the Vector dialect layer.
2025-07-09 12:09:17 -07:00
Daniel Hernandez-Juarez
668c964282
[AMDGPU] [MLIR] Add 96 and 128 bit GatherToLDS for gfx950 (#147496)
This PR adds 96 and 128 gather_to_lds support for gfx950. Updating
lowering, verifier and tests.
2025-07-09 11:53:26 -04:00
MaheshRavishankar
c22352175e
[mlir][TilingInterface] Allow tile and fuse to work with ReductionTilingStrategy::PartialReductionOuterParallelStrategy. (#147593)
Since `scf::tileUsingSCF` is the core method used for tiling the root
operation within the `scf::tileConsumersAndFuseProducersUsingSCF`, the
latter can fuse into any tiled loop generated using `scf::tileUsingSCF`.
This patch adds a test for tiling a root operation using
`ReductionTilingStrategy::PartialReductionOuterParallelStrategy` and
fusing producers with it.

Since this strategy generates a rank-reducing extract slice
`tensor::replaceExtractSliceWithTiledProducer` which is the core method
used for the fusion was extended to handle the rank-reducing slices.

Also fix a small bug in the computation of the reduction induction
variable (which needs to use `floorDiv` instead of `ceilDiv`)

Signed-off-by: MaheshRavishankar <mahesh.ravishankar@gmail.com>
2025-07-09 08:50:01 -07:00
Mohammadreza Ameri Mahabadian
f92420078e
[mlir][spirv] TableGen definition SPIRV_Composite to include SPIRV_AnyTensorArm (#147567)
SPIRV_AnyTensorArm is a recently added composite type. This patch adds
to the list of composite type represented by SPIRV_Composite. This was
missing from a previous
[patch](https://github.com/llvm/llvm-project/pull/144667) where
SPIRV_AnyTensorArm was introduced.

Signed-off-by: Mohammadreza Ameri Mahabadian <mohammadreza.amerimahabadian@arm.com>
2025-07-09 11:49:37 -04:00
Maksim Levental
1770e9b5c6
[mlir] remove dangling builders from td (#147619)
These are "dangling" builders (decls are emitted but there are no defns
anywhere).
2025-07-09 09:59:24 -04:00
Mehdi Amini
fbb2fa92cb [MLIR] Add missing includes
The build was broken when MLIR_NVVM_EMBED_LIBDEVICE was enabled.
2025-07-09 03:49:02 -07:00
Momchil Velikov
962c4217bc
[MLIR][AArch64] Change some tests to ensure SVE vector length is the same throughout the function (#147506)
This change only applies to functions the can be reasonably expected to
use SVE registers.

Modifying vector length in the middle of a function might cause
incorrect stack deallocation if there are callee-saved SVE registers or
incorrect access to SVE stack slots.

Addresses (non-issue) https://github.com/llvm/llvm-project/issues/143670
2025-07-09 09:32:25 +01:00
zbenzion
6033544173
[mlir][linalg] Fix memref type verification in CollapseLinalgDimensions (#147245)
When collapsing linalg dimensions we check if its memref operands are
guaranteed to be collapsible. However, we currently assume that the
matching indexing map is the identity map.

This commit modifies this behavior and checks if the memref is
collapsible on the transformed dimensions.
2025-07-09 01:04:08 -07:00
Menooker
18b409558a
[mlir] [scf-to-cf] attach the loop annotation to latch block (#147462)
As [required by LLVM](https://llvm.org/docs/LangRef.html#llvm-loop), the
loop annotation (loop metadata) should be attached on the ["latch"
block](https://llvm.org/docs/LoopTerminology.html). Otherwise, the
annotation might be ignored by LLVM. This PR fixes this issue.
2025-07-09 12:07:35 +08:00
Michael Liao
55e1e9c96f [mlir][llvm] Fix typo 2025-07-08 19:33:04 -04:00
Kazu Hirata
57d2d89241
[mlir] Remove unused includes (NFC) (#147549)
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.
2025-07-08 12:47:30 -07:00
Tim Gymnich
6f291cb099
[mlir][amdgpu] Add conversion from arith.scaling_extf / arith.scaling_truncf to amdgpu (#146372)
- add conversion from arith.scaling_extf to amdgpu.scaled_ext_packed
- add conversion from arith.scaling_truncf to amdgpu.packed_scaled_trunc
2025-07-08 21:45:23 +02:00
agozillon
71783fea2c [Flang][OpenMP][MLIR] Fix regression by #146653 by adding address space cast to getRefPtrIfDeclareTarget
The patch introduced changes to add address spaces to a wider array of MLIR/LLVM values, however,
it was missing an address space cast that exists in our downstream implementation that's required
for declare target to work correctly.
2025-07-08 12:31:27 -05:00
Darren Wihandi
4a68562e9a
[mlir][spirv] Reject coop matrix operands on unsupported arithmetic ops (#147230)
Cooperative matrix operands are only supported for `add/sub/mul/div`
binary arithmetic ops, but currently all binary arithmetic ops accept
cooperative matrix operands, including `mod/rem`. This change fixes this
behaviour.
2025-07-08 10:44:37 -04:00
lonely eagle
517cda12e5
[mlir][vector] Add foldInsertUseChain folder function to insert op (#147045)
When the result of an insert op is used by an insert op, and the
subsequent insert op is inserted at the same location as the previous
insert op, replaces the dest of the subsequent insert op with the dest
of the previous insert op.This is because the previous insert op does
not affect subsequent insert ops.

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
Co-authored-by: Andrzej Warzyński <andrzej.warzynski@gmail.com>
2025-07-08 22:39:18 +08:00
Kajetan Puchalski
9006bc8717
[OpenMP] Enable simd in non-reduction composite constructs (#146097)
Despite currently being ignored with a warning, simd as a leaf in
composite constructs behaves as expected when the construct does not
contain a reduction. Enable it for those non-reduction constructs.

---------

Signed-off-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
2025-07-08 14:27:33 +01:00
Rolf Morel
db7888ca9a
[MLIR][Transform] Introduce transform.tune.knob op (#146732)
A new transform op to represent that an attribute is to be chosen from a
set of alternatives and that this choice is made available as a
`!transform.param`. When a `selected` argument is provided, the op's
`apply()` semantics is that of just making this selected attribute
available as the result. When `selected` is not provided, `apply()`
complains that nothing has resolved the non-determinism that the op is
representing.
2025-07-08 11:00:34 +01:00
Niklas Degener
dcc692a42f
[MLIR][Target/Cpp] Natural induction variable naming. (#136102)
Changed naming of loop induction variables to follow natural naming (i,
j, k, ...). This helps readability and locating positions referred to.
Created new scopes to represent different behavior at function and loop
level, to still enable re-using value names between different functions
(as before). Removed unused scoping at other levels.
2025-07-08 09:18:00 +02:00
Kazu Hirata
54bd936ec9
[mlir] Remove unused includes (NFC) (#147455)
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.
2025-07-07 23:40:44 -07:00
Jakub Kuderski
6512ca7ddb
[mlir] Add isStatic* size check for ShapedTypes. NFCI. (#147085)
The motivation is to avoid having to negate `isDynamic*` checks, avoid
double negations, and allow for `ShapedType::isStaticDim` to be used in
ADT functions without having to wrap it in a lambda performing the
negation.

Also add the new functions to C and Python bindings.
2025-07-07 14:57:27 -04:00
Diego Caballero
7451e4c330
[mlir][Vector] Support scalar 'vector.insert' in vector linearization (#146954)
This PR add support for linearizing the insertion of a scalar element by
just linearizing the `vector.insert` op.
2025-07-07 10:22:33 -07:00
Nicolas Vasilache
c30b5b1549
[mlir][GPU][transform] Add gpu_to_rocdl conversion pattern (#146962)
Co-authored-by: Son Tuan Vu <vuson@google.com>
2025-07-07 18:34:09 +02:00
Nicolas Vasilache
2b28d10022
[mlir][SCF][GPU] Add DeviceMaskingAttrInterface (#146943)
This revision adds DeviceMaskingAttrInterface and extends
DeviceMappingArrayAttr to accept a union of DeviceMappingAttrInterface
and DeviceMaskingAttrInterface.

Support is added to GPUTransformOps to take advantage of this
information and lower to block/warpgroup/warp/thread specialization when
mapped to linear ids.

The revision also connects to scf::ForallOp and uses the new attribute
to implement warp specialization.
The implementation is in the form of a GPUMappingMaskAttr, which can be
additionally passed to the scf.forall.mapping attribute to specify a
mask on compute resources that should be active.

In the first implementation the masking is a bitfield that specifies for
each processing unit whether it is active or not.
In the future, we may want to implement this as a symbol to refer to
dynamically defined values.
Extending op semantics with an operand is deemed too intrusive at this
time.

---------

Co-authored-by: Oleksandr "Alex" Zinenko <git@ozinenko.com>
2025-07-07 18:06:41 +02:00
Nicolas Vasilache
ea62de5b1d
[mlir] NFC - refactor id builder and avoid leaking impl details (#146922) 2025-07-07 15:42:48 +02:00
Nikita Popov
c3c3919dc2 Revert "[DenseMap] Do not align pointer sentinel values (NFC) (#146595)"
This reverts commit 7a6435bec59010e4bb2e1e52a9ba840ed152b4ce.

This causes ubsan failures when the sentinel pointers are upcast
using static_cast<>, which checks alignment.
2025-07-07 15:15:47 +02:00
Nicolas Vasilache
0a62836969
[mlir][gpu][transforms] Add support for mapping to lanes (#146912)
This revision adds a new attribute for mapping `scf.forall` to linear
lane ids.

Example:
```
    // %arg2 and %arg3 map to lanes [0, 6) and are turned into epxressions
    // involving threadIdx.x/y by the map_nested_forall_to_threads
    // transformation. This results in a if (linear_thread_id < 6) conditional.
    scf.forall (%arg2, %arg3) in (2, 3) {
       ...
    } {mapping = [#gpu.lane<linear_dim_0>, #gpu.lane<linear_dim_1>]}
 ```

---------

Co-authored-by: Oleksandr "Alex" Zinenko <git@ozinenko.com>
2025-07-07 15:14:52 +02:00
Renato Golin
6daf2b956d
[MLIR][Linalg] Remove elemwise_unary and elemwise_binary (#147082)
RFC:
https://discourse.llvm.org/t/rfc-deprecate-linalg-elemwise-unary-and-elemwise-binary/87144

Remove the two operations and fix the tests by:
* Cleaning simple operation tests of the old ops
* Changing `linalg.elemwise_{u|bi}nary` with `linalg.{exp|add}` on
transform tests
* Changing some of the tests with `linalg.elementwise` instead, to
broaden test coverage
* Surgically removing the `elemwise_*` part in the Python tests
* Update MLIR transform examples (text and tests) with
`linalg.elementwise` instead

Nothing else changed.
2025-07-07 12:33:55 +01:00
Robert Konicar
0aab8e4ccc
[MLIR][LLVM][NFC] Remove unused argument from parseOptionalLLVMKeyword (#147058) 2025-07-07 13:29:04 +02:00
Nikita Popov
7a6435bec5
[DenseMap] Do not align pointer sentinel values (NFC) (#146595)
DenseMapInfo for pointers currently uses empty/tombstone values that are
aligned (by assuming a very conservative alignment). However, this means
that we have to work with larger immediates.

This patch proposes to use the values -1 and -2 instead, without caring
about pointer alignment. (Non-roundtrip) integer to pointer casts are
implementation-defined in C++, but the general implementer consensus
(including Clang) is that raw pointers do not carry alignment
requirements, only memory accesses do.

We already have lots of places that rely on this using variations on
`reinterpret_cast<T*>(-1)`, so it seems odd to insist on properly
aligned pointers in this one place.

It is necessary to adjust a few other places after this change, which
currently assume that `DenseMapInfo<void *>` returns a highly-aligned
pointer.

This is a small improvement for both compile-time and clang binary size.
2025-07-07 12:47:41 +02:00
Igor Wodiany
de7ff1f224
[mlir][spirv][nfc] Add StorageImageReadWithoutFormat capability to the Target test (#145949)
The serialized SPIR-V would not validate as the capability required for
Unknown format in the image read was missing.
2025-07-07 10:45:36 +01:00
Igor Wodiany
b6b2561337
[mlir][spirv] Add support for Aligned memory operand in CoopMatrix memory operations (#145480)
In the process of adding support for Aligned, I have noticed that the
support for `MakePointerAvailable` and `MakePointerVisible` is
incomplete as the operation does not accept a scope nor check for
`NonPrivatePointer`. The PR does not address it, but the relevant issues
has been created #145485.
2025-07-07 10:44:43 +01:00
Kazu Hirata
be4cd9f4da
[mlir] Remove unused includes (NFC) (#147206)
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.
2025-07-06 19:06:07 -07:00
Longsheng Mou
5a8e60e724
[mlir] Use llvm::fill instead of std::fill(NFC) (#146889) 2025-07-07 09:12:38 +08:00