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Author	SHA1	Message	Date
Nashe Mncube	d4f38f43f5	[LLVM][ARM][CodeGen]Define branch instruction alignment for m85 and m7 (#109647 ) Branch instruction alignments were not defined for cortex-m85 and cortex-m7 which misses an optimisation opportunity. With this patch we see performance improvements as high as 5% on some benchmarks with most around 1%.	2024-09-24 11:26:06 +01:00
Nicholas Guy	d65feccb12	[ARM] Set preferred function alignment Aligning functions yields small performance gains on embedded cores, moreso with numerous small function calls. Similar to aligning loops, if the function can fit within a single cache line then the performance overhead of fetching more instructions can be limited. Differential Revision: https://reviews.llvm.org/D157514	2023-08-16 17:31:21 +01:00

Author

SHA1

Message

Date

Nashe Mncube

d4f38f43f5

[LLVM][ARM][CodeGen]Define branch instruction alignment for m85 and m7 (#109647 )

Branch instruction alignments were not defined for cortex-m85 and
cortex-m7 which misses an optimisation opportunity. With this patch we
see performance improvements as high as 5% on some benchmarks with most
around 1%.

2024-09-24 11:26:06 +01:00

Nicholas Guy

d65feccb12

[ARM] Set preferred function alignment

Aligning functions yields small performance gains on
embedded cores, moreso with numerous small function calls.
Similar to aligning loops, if the function can fit within
a single cache line then the performance overhead of
fetching more instructions can be limited.

Differential Revision: https://reviews.llvm.org/D157514

2023-08-16 17:31:21 +01:00

2 Commits