37770 Commits

Author SHA1 Message Date
Tim Gymnich
760bf4f116
[GISel] Add KnownFPClass Analysis to GISelValueTrackingPass (#134611)
- add KnownFPClass analysis to GISelValueTrackingPass
- add MI pattern for `m_GIsFPClass`
2025-05-23 14:38:51 +02:00
Kazu Hirata
cc78177e8f
[llvm] Use *Map::try_emplace (NFC) (#141190)
try_emplace can default-construct values, so we do not need to do so
on our own.  Plus, try_emplace(Key) is much simpler/shorter than
insert({Key, LongValueType()}).
2025-05-22 23:50:58 -07:00
Tim Gymnich
ed75e2114f
Fix build for GenericFloatingPointPredicateUtils #140254 (#141095)
Fixes linker issue with #140254  / #140254
2025-05-22 18:02:11 +02:00
Craig Topper
c432936b05
[SelectionDAG][RISCV] Use VP_STORE to widen MSTORE in type legalization when possible. (#140991)
Widening the mask and padding with zeros doesn't work for scalable
vectors. Using VL produces less code for fixed vectors.

Similar was recently done for MLOAD.
2025-05-22 08:28:42 -07:00
Tim Gymnich
571a24c314
Reland [llvm] add GenericFloatingPointPredicateUtils #140254 (#141065)
#140254 was previously missing 2 files in the bazel build config.
2025-05-22 17:17:02 +02:00
Rahul Joshi
1fdf02ad5a
[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties (#140002)
Add per-property has<Prop>/set<Prop>/reset<Prop> functions to
MachineFunctionProperties.
2025-05-22 08:07:52 -07:00
Orlando Cazalet-Hyams
34a55c9376
[BranchFolding] Fix assertion failure in HoistCommonCodeInSuccs (#141028)
Assertion failure introduced in #140063, which didn't account for TBB
and FBB being the same block.
2025-05-22 13:21:26 +01:00
Pierre van Houtryve
b5e2a236b9
[CodeGen] Add SSID & Atomic Ordering to IntrinsicInfo (#140896)
getTgtMemIntrinsic should be able to propagate such information to the
MMO
2025-05-22 11:42:01 +02:00
Luke Lau
09c3d1432b
[IA] Add support for [de]interleave{3,5,7} (#139373)
This adds support for lowering deinterleave and interleave intrinsics
for factors 3 5 and 7 into target specific memory intrinsics.

Notably this doesn't add support for handling higher factors constructed
from interleaving interleave intrinsics, e.g. factor 6 from interleave3
+ interleave2.

I initially tried this but it became very complex very quickly. For
example, because there's now multiple factors involved
interleaveLeafValues is no longer symmetric between interleaving and
deinterleaving. There's then also two ways of representing a factor 6
deinterleave: It can both be done as either 1 deinterleave3 and 3
deinterleave2s OR 1 deinterleave2 and 3 deinterleave3s.

I'm not sure the complexity of supporting arbitrary factors is warranted
given how we only need to support a small number of factors currently:
SVE only needs factors 2,3,4 whilst RVV only needs 2,3,4,5,6,7,8.

My preference would be to just add a interleave6 and deinterleave6
intrinsic to avoid all this ambiguity, but I'll defer this discussion to
a later patch.
2025-05-22 04:32:47 +01:00
Craig Topper
0a42db682a [SelectionDAG] Simplify creation of getStoreVP in WidenVecOp_STORE. NFC
We can use the offset from the original store instead of creating
a new undef offset.

We didn't check if the offset was undef already so we really shouldn't
drop it if it isn't.
2025-05-21 17:46:08 -07:00
Kewen12
c47a5fbb22
Revert "[llvm] add GenericFloatingPointPredicateUtils (#140254)" (#140968)
This reverts commit d00d74bb2564103ae3cb5ac6b6ffecf7e1cc2238. 

The PR breaks our buildbots and blocks downstream merge.
2025-05-21 19:31:14 -04:00
Craig Topper
60ad6e3fa4
[SelectionDAG][RISCV] Use VP_LOAD to widen MLOAD in type legalization when possible. (#140595)
Padding the mask using 0 elements doesn't work for scalable vectors. Use
VP_LOAD and change the VL instead.

This fixes crash for Zve32x. Test file was split since i64 isn't a valid
element type for Zve32x.

Fixes #140198.
2025-05-21 15:52:08 -07:00
Tim Gymnich
d00d74bb25
[llvm] add GenericFloatingPointPredicateUtils (#140254)
add `GenericFloatingPointPredicateUtils` in order to generalize
effects of floating point comparisons on `KnownFPClass` for both IR and
MIR.

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2025-05-21 23:45:31 +02:00
Craig Topper
ee4002da2b [TargetLowering] Use getExtractSubvector/getExtractVectorElt. NFC 2025-05-21 12:06:54 -07:00
David Green
77c8d21413
[GlobalISel] Fix ZExt known bits for scalable vectors. (#140213)
It was using the full size of the vector as the SrcBitWidth. This patch
changes the code to split G_ASSERT_ZEXT away from the others (G_INTTOPTR
/ G_PTRTOINT / G_ZEXT / G_TRUNC) which are simpler, and make the code
match the SDAG equivalent.
2025-05-21 19:52:19 +01:00
Matt Arsenault
2e2bbcacf8
AMDGPU/GlobalISel: Start legalizing minimumnum and maximumnum (#140900)
This is the bare minimum to get the intrinsic to compile for AMDGPU,
and it's not optimal. We need to follow along closer with the existing
G_FMINNUM/G_FMAXNUM with custom lowering to handle the IEEE=0 case
better.

Just re-use the existing lowering for the old semantics for
G_FMINNUM/G_FMAXNUM. This does not change G_FMINNUM/G_FMAXNUM's
treatment,
nor try to handle the general expansion without an underlying min/max
variant (or with G_FMINIMUM/G_FMAXIMUM).
2025-05-21 17:00:45 +02:00
Kazu Hirata
fe6290ef5b
[llvm] Use *Map::try_emplace (NFC) (#140843)
try_emplace can default-construct values, so we do not need to do so
on our own.  Plus, try_emplace(Key) is much shorter than
insert(std::make_pair(Key, Value()).
2025-05-21 01:11:01 -07:00
Kazu Hirata
1fd24369c3
[CodeGen] Use range-based for loops (NFC) (#140840) 2025-05-20 21:39:59 -07:00
Kazu Hirata
51b288d9cf
[CodeGen] Avoid repeated hash lookups (NFC) (#140838) 2025-05-20 21:39:17 -07:00
Alan Li
ada2fbfe36
[GISel] Fix ShuffleVector assert (#139769)
Fixes issue: https://github.com/llvm/llvm-project/issues/139752

When G_SHUFFLE_VECTOR has only 1 element then it is possible the vector
is decayed into a scalar.
2025-05-20 21:25:31 -04:00
Andrew Rogers
98595cfd6f
[llvm] prepare explicit template instantiations in llvm/CodeGen for DLL export annotations (#140653)
## Purpose

This patch prepares the llvm/CodeGen library for public interface
annotations in support of an LLVM Windows DLL (shared library) build,
tracked in #109483. The purpose of this patch is to make the upcoming
codemod of this library more straight-forward. It is not expected to
impact any functionality.

The `LLVM_ABI` annotations will be added in a subsequent patch. These
changes are required to build with visibility annotations using Clang
and gcc on Linux/Darwin/etc; Windows DLL can build fine without them.

## Overview
This PR does four things in preparation for adding `LLVM_ABI`
annotations to llvm/CodeGen:
1. Explicitly include `Machine.h` and `Function.h` headers from
`MachinePassManager.cpp` so that `Function` and `Machine` types are
available for the instantiations of `InnerAnalysisManagerProxy`. Without
this change, Clang only will only export one of the templates after
visibility annotations are added to them. Unclear if this is a Clang bug
or expected behavior, but this change avoids the issue and should be
harmless.
2. Refactor the definition of `MachineFunctionAnalysisManager` to its
own header file. Without this change, it is not possible to add
visibility annotations to the declaration with causing gcc to produce
`-Wattribute` warnings.
3. Remove the redundant specialization of the
`DominatorTreeBase<MachineBasicBlock, false>::addRoot` method. The
specialization is the same as implemented in `DominatorTreeBase` so
should be unnecessary. Without this change, it is not possible to
annotate the subsequent instantiations of `DominatorTreeBase` in the
header file without gcc producing `-Wattribute` warnings. Mark
unspecialized `addRoot` as `inline` to match the removed specialized
version.
4. Move the explicit instantiations of the `GenericDomTreeUpdater`
template earlier in the header file. These need to appear before being
used in the `MachineDomTreeUpdater` class definition or gcc will produce
warnings once visibility annotations are added.

## Background

The LLVM Windows DLL effort is tracked in #109483. Additional context is
provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).

Clang and gcc handle visibility attributes on explicit template
instantiations a bit differently; gcc is pickier and generates
`-Wattribute` warnings when an explicit instantiation with a visibility
annotation appears after the type has already appeared in the
translation unit. These warnings can be avoided by moving explicit
template instantiations so they always appear first.

## Validation

Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:

- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
2025-05-20 14:40:20 -07:00
David Green
85a6bedf00
[GlobalISel] Add known bits and sign-bits handling for G_SPLAT_VECTOR (#140204)
This forwards the KnownBits / SignBits from the scalar operand through
to the vector elements. The value is implicitly truncated if it is
larger than the vector element size. The change in
GISelValueTracking::computeNumSignBits allows scalable sign-bits using a
single element demanded elts, and brings it in line with the code in
ValueTracking and SDAG (and GISelValueTracking::getKnownBits). That was
the main motivation for adding this opcode, to prevent scalable vector
asserts.
2025-05-20 12:42:20 +01:00
Paul Walker
5dfaf8418d
[LLVM][AArch64] Correctly lower funnel shifts by constants. (#140058)
Prevent LowerFunnelShift from creating an invalid ISD::FSHR when
lowering "ISD::FSHL X, Y, 0". Such inputs are rare because it's a NOP
that DAGCombiner will optimise away. However, we should not rely on this
and so this PR mirrors the same optimisation.
    
Ensure LowerFunnelShift normalises constant shift amounts because isel
rules expect them to be in the range [0, src bit length).
    
NOTE: To simiplify testing, this PR also adds a command line option to
disable the DAG combiner (-combiner-disabled).
2025-05-20 11:15:21 +01:00
Orlando Cazalet-Hyams
4060d38746
[BranchFolding] Merge debug locs on common hoisted code (#140063)
branch-folder hoists common instructions from TBB and FBB into their
pred. Without this patch it achieves this by splicing the instructions from TBB
and deleting the common ones in FBB. That moves the debug locations and debug
instructions from TBB into the pred without modification, which is not
ideal. The merged instructions should get merged debug locations for debugging
and PGO purposes, which is handled in this patch. Debug instructions also need
to be handled differently. That'll come in another patch. This issue was found
by @omern1.
2025-05-20 11:11:45 +01:00
Benjamin Maxwell
c9d6249198
[SDAG] Ensure load is included in output chain of sincos expansion (#140525)
The load not being included in the chain meant that it could materialize
after a `@llvm.lifetime.end` annotation on the pointer. This could
result in miscompiles if the stack slot is reused for another value.

Fixes https://github.com/llvm/llvm-project/issues/140491
2025-05-20 10:43:50 +01:00
David Green
b95ad8eca6
[DAGCombine] Use isLegalExtLoad for MatchLoadCombine (#140536)
This looks wrong to me, but I don't have a test case where it alters the
generated code.
2025-05-20 09:59:41 +01:00
David Green
d644597f57
[GlobalISel] Add computeNumSignBits for G_SHUFFLE_VECTOR (#139505)
The code is similar to computeKnownBits and the code in
SelectionDAG::ComputeNumSignBits.
2025-05-20 08:25:48 +01:00
Kazu Hirata
a754bc27e4
[CodeGen] Avoid repeated map lookups (NFC) (#140662) 2025-05-19 21:36:31 -07:00
Iris Shi
bdf03fcff3
Revert "[llvm][NFC] Use llvm::sort()" (#140668) 2025-05-20 11:27:03 +08:00
Alexander Richardson
07e2ba445d
[AMDGPU] Set AS8 address width to 48 bits
Of the 128-bits of buffer descriptor only 48 bits are address bits, so
following the discussion on https://discourse.llvm.org/t/clarifiying-the-semantics-of-ptrtoint/83987/54,
the logic conclusion is to set the index width to 48 bits instead of
the current value of 128.

Most of the test changes are mechanical datalayout updates, but there
is one actual change: the ptrmask test now uses .i48 instead of .i128
and I had to update SelectionDAGBuilder to correctly extend the mask.

Reviewed By: krzysz00

Pull Request: https://github.com/llvm/llvm-project/pull/139419
2025-05-19 17:26:05 -07:00
Liam Semeria
d067014f13
[APInt] Added APInt::clearBits() method (#137098)
Added APInt::clearBits(unsigned loBit, unsigned hiBit) that clears bits within a certain range.

Fixes #136550

---------

Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
2025-05-19 12:41:04 +01:00
Kazu Hirata
d1cd68881a
[llvm] Use llvm::is_sorted (NFC) (#140399) 2025-05-17 14:29:35 -07:00
David Green
fcef8a471e
[GlobalISel] Put legalizer rule debug behind a verbose option. (#138277)
With the large number of G_ opcodes now present, this debug information
emitted for checking the global isel legalizer rules are valid is quite
verbose and runs even when gisel is not being used. This makes it
especially verbose when running a single pass with -debug.

This patch puts it behind a verbose debug option so that most people
don't need to worry about it.
2025-05-17 16:48:44 +01:00
Matthias Braun
252ba8e3fb
NFC: Refactor MIRPrinter into state struct and functions (#140317)
Moves `MIRPRinter` and `MIPrinter` fields into a new `MFPrintState`
struct. Turns methods into independent functions.

- This slightly simplifies the code.
- In the future this will allow to pass the state around to other printing functions
   without the need to expose classes in the public headers.
2025-05-17 08:08:12 -07:00
David Green
722385e87b
[GlobalISel] Add G_SHUFFLE_VECTOR computeKnownBits (#139501)
The code is taken from SelectionDAG::computeKnownBits.
2025-05-17 12:20:16 +01:00
Piotr Fusik
9e22f9611a
[DAGCombiner] Fix a "subtraction if above a constant threshold" miscompile (#140042)
This fixes #135194 incorrectly reusing the existing `add nuw/nsw`
while the transformed code relies on an unsigned wrap.
2025-05-17 12:18:52 +02:00
Kazu Hirata
e1cee35546
[CodeGen] Use llvm::lower_bound (NFC) (#140341) 2025-05-16 23:53:20 -07:00
Iris Shi
061a7699f3
[llvm][NFC] Use llvm::sort() (#140335) 2025-05-17 14:49:46 +08:00
Craig Topper
aaaae99663 [SelectionDAG] Use getInsertSubvector/VectorElt and getExtractSubvector/VectorElt in LegalizeVectorTypes. NFC 2025-05-16 23:37:03 -07:00
Philip Reames
3def9976eb Use early return/continue in TailDuplicator::duplicateInstruction [nfc] 2025-05-16 13:33:11 -07:00
Craig Topper
dcd62f3674
[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)
This matches the underlying function in MachineMemOperand and how it is
printed when BaseAlign differs from Align.
2025-05-16 09:37:02 -07:00
Jay Foad
e30301aaec
[MachineCopyPropagation] Make use of lane mask info in basic block liveins (#140248) 2025-05-16 16:54:34 +01:00
Pierre van Houtryve
5e7bc5e080
[DAGCombiner] Remove hasOneUse check from sext+sext_inreg to sext_inreg combine (#140207)
The hasOneUseCheck does not really add anything and makes the combine too
restrictive. Upcoming patches benefit from removing the hasOneUse check.
2025-05-16 10:25:49 +02:00
Oliver Hunt
39fa5b31c5
[llvm][NFC] Update LocalVarDef::CVRegister to fix size MS ABI (#140214)
LocalVarDef::CVRegister being a uint16_t is not enough for the fields to
be packed with the MS ABI.

This makes the field a 16 bit a uint32_t
2025-05-16 00:47:52 -07:00
Oliver Hunt
76ba29bfd8
[NFC] Address bit-field storage sizes to ensure ideal packing (#139825)
The MS bit-field packing ABI depends on the storage size of the type of
being placed in the bit-field. This PR addresses a number of cases in
llvm where the storage type has lead to suboptimal packing.
2025-05-16 00:02:58 -07:00
Kazu Hirata
6033a4859a
[CodeGen] Use std::tie to implement a comparison functor (NFC) (#140088)
std::tie simplifies the lexicographical comparison while making the
code a little more consistent within MIRPrinter.cpp as we have a very
similar comparison functor in MIRPrinter::convertCalledGlobals, about
30 lines below the code this patch touches.
2025-05-15 12:18:54 -07:00
Kazu Hirata
18ecff4f65
[llvm] Use llvm::stable_sort (NFC) (#140067) 2025-05-15 12:18:18 -07:00
Alexander Peskov
2bc9f43ba1
[DAGCombiner] Fold pattern for srl-shl-zext (REAPPLIED) (#140038)
Fold (srl (lop x, (shl (zext y), c1)), c1) -> (lop (srl x, c1), (zext y)) where c1 <= leadingzeros(zext(y)).

This is equivalent of existing fold chain (srl (shl (zext y), c1), c1) -> (and (zext y), mask) -> (zext y), but logical op in the middle prevents it from combining.

Profit : Allow to reduce the number of instructions.

Original commit: #138290 / bbc5221

Previously reverted due to conflict in LIT test. Mainline changed
default version of load instruction to untyped version by this #137698 .
Updated test uses `ld.param.b64` instead of `ld.param.u64`.
2025-05-15 18:04:33 +01:00
weiguozhi
59c6d70ed8
[CodeGenPrepare] Make sure instruction get from SunkAddrs is before MemoryInst (#139303)
Function optimizeBlock may do optimizations on a block for multiple
times. In the first iteration of the loop, MemoryInst1 may generate a
sunk instruction and store it into SunkAddrs. In the second iteration of
the loop, MemoryInst2 may use the same address and then it can reuse the
sunk instruction stored in SunkAddrs, but MemoryInst2 may be before
MemoryInst1 and the corresponding sunk instruction. In order to avoid
use before def error, we need to find appropriate insert position for the
 sunk instruction.

Fixes #138208.
2025-05-15 09:27:25 -07:00
Kazu Hirata
9658c55116 [SelectionDAG] Fix a warning
This patch fixes:

  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7506:17: error:
  unused variable 'NoFPClass' [-Werror,-Wunused-variable]
2025-05-15 07:05:33 -07:00