24952 Commits

Author SHA1 Message Date
Alexey Bataev
931bba2bc3 [SLP][NFC]Add a test with reused scalars in 3 tree nodes with different
VF, NFC.
2023-03-02 10:50:03 -08:00
Sanjay Patel
6956788cbd [InstCombine] add tests for absolute diff; NFC
More coverage for D145073.
2023-03-02 11:24:09 -05:00
Nikita Popov
d3ac92f1e1 [GlobalOpt] Regenerate test checks (NFC)
And drop the unnecessary main function.
2023-03-02 17:07:58 +01:00
chenglin.bi
97dcbea63e [LogicCombine 1/?] Implement a general way to simplify logical operations.
This patch involves boolean ring to simplify logical operations. We can treat `&` as ring multiplication and `^` as ring addition.
So we need to canonicalize all other operations to `*` `+`. Like:
```
a & b -> a * b
a ^ b -> a + b
~a -> a + 1
a | b -> a * b + a + b
c ? a : b -> c * a + (c + 1) * b
```
In the code, we use a mask set to represent an expression. Every value that is not comes from logical operations could be a bit in the mask.
The mask itself is a multiplication chain. The mask set is an addiction chain.
We can calculate two expressions based on boolean algebras.

For now, the initial patch only enabled on and/or/xor,  Later we can enhance the code step by step.

Reference: https://en.wikipedia.org/wiki/Boolean_ring

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D142803
2023-03-02 20:46:16 +08:00
J. Ryan Stinnett
0bbe6040be [DebugInfo] Remove dbg.addr from Transforms
Part of `dbg.addr` removal
Discussed in https://discourse.llvm.org/t/what-is-the-status-of-dbg-addr/62898

Differential Revision: https://reviews.llvm.org/D144797
2023-03-02 09:29:43 +00:00
J. Ryan Stinnett
29a6b7dfae [DebugInfo] Remove dbg.addr from Coroutines
This removes `dbg.addr` support from the Coroutines transform. This effectively
reverts the `dbg.addr`-only portions of 19279ffc77b8d224c447d4eb0ee0c727ab64babf
and 0b647fc5299156bf83c46aa539d6c9c39647bb36.

Part of `dbg.addr` removal
Discussed in https://discourse.llvm.org/t/what-is-the-status-of-dbg-addr/62898

Differential Revision: https://reviews.llvm.org/D144795
2023-03-02 09:29:42 +00:00
Florian Hahn
d94e8479fc
[GlobalOpt] Extend CleanupPointerRootUsers to handle CE users.
Extend CleanupPointerRootUsers to iterate over a worklist, add users of
constant expressions to the worklist to enable additional cleanups.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D144468
2023-03-02 10:12:24 +01:00
Zhongyunde
af2969fd46 Revert "[MergeICmps] Adapt to non-eq comparisons, retry"
This reverts commit 74ad19c25d7217d8f580a21d12fd4c784a1a0094.

test unittests/ProfileData/ProfileDataTests fails when built with
optimisations level -O1 with clang including this patch.
2023-03-02 09:07:44 +08:00
Sanjay Patel
6c7b2eef47 [PhaseOrdering] add test for vector load and cast transforms; NFC
issue #51397
2023-03-01 13:07:16 -05:00
Sanjay Patel
cf53bd8ca2 [InstCombine] add tests for signed absolute diff; NFC 2023-03-01 13:07:16 -05:00
Alexey Bataev
4e4ad3ab0e [SLP][NFC]Update the test to simplify and avoid dead instruction
removal, NFC.
2023-03-01 06:35:56 -08:00
Mel Chen
9d0703a646 [RISCV] Pre-commit test case for ordered reduction, NFC
Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D144458
2023-03-01 06:27:43 -08:00
Sander de Smalen
c41b41eb11 [LoopVectorize] Use overflow-check analysis to improve tail-folding.
This work follows on from D142109 and addresses a possible regression
when we know the loop iteration counter cannot overflow.

When we know the overflow-check always evaluates to false, it's better to
use the other style of tail folding where it assumes a runtime check was
added, because that avoids having to calculate a modified trip-count.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D142894
2023-03-01 14:17:58 +00:00
Sanjay Patel
452279efe2 [InstCombine] prevent miscompiles from select-of-div/rem transform
This avoids the danger shown in issue #60906.
There were no regression tests for these patterns, so these potential
failures have been around for a long time.

We freeze the condition and preserve the optimization because
getting rid of a div/rem is always a win.

Here are a couple of examples that can be corrected by freezing the
condition:
https://alive2.llvm.org/ce/z/sXHTTC

Differential Revision: https://reviews.llvm.org/D144671
2023-03-01 08:54:23 -05:00
Zhongyunde
15d5c59280 [InstCombine] Improvement the analytics through the dominating condition
Address the dominating condition, the urem fold is benefit from the analytics improvements.
Fix https://github.com/llvm/llvm-project/issues/60546

NOTE: delete the calls in simplifyBinaryIntrinsic and foldICmpWithDominatingICmp
is used to reduce compile time.

Reviewed By: nikic, arsenm, erikdesjardins
Differential Revision: https://reviews.llvm.org/D144248
2023-03-01 17:03:34 +08:00
Sander de Smalen
fe1b51ffee [LoopVectorize] Remove runtime check and scalar tail loop when tail-folding.
When using tail-folding and using the predicate for both data and control-flow
(the next vector iteration's predicate is generated with the llvm.active.lane.mask
intrinsic and then tested for the backedge), the LoopVectorizer still inserts a
runtime check to see if the 'i + VF' may at any point overflow for the given
trip-count. When it does, it falls back to a scalar epilogue loop.

We can get rid of that runtime check in the pre-header and therefore also
remove the scalar epilogue loop. This reduces code-size and avoids a runtime
check.

Consider the following loop:

  void foo(char * __restrict__ dst, char *src, unsigned long N) {
      for (unsigned long  i=0; i<N; ++i)
          dst[i] = src[i] + 42;
  }

If 'N' is e.g. ULONG_MAX, and the VF > 1, then the loop iteration counter
will overflow when calculating the predicate for the next vector iteration
at some point, because LLVM does:

  vector.ph:
    %active.lane.mask.entry = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 %N)

  vector.body:
    %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
    %active.lane.mask = phi <vscale x 16 x i1> [ %active.lane.mask.entry, %vector.ph ], [ %active.lane.mask.next, %vector.body ]
    ...

    %index.next = add i64 %index, 16
      ; The add above may overflow, which would affect the lane mask and control flow. Hence a runtime check is needed.
    %active.lane.mask.next = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 %index.next, i64 %N)
    %8 = extractelement <vscale x 16 x i1> %active.lane.mask.next, i64 0
    br i1 %8, label %vector.body, label %for.cond.cleanup, !llvm.loop !7

The solution:

What we can do instead is calculate the predicate before incrementing
the loop iteration counter, such that the llvm.active.lane.mask is
calculated from 'i' to 'tripcount > VF ? tripcount - VF : 0', i.e.

  vector.ph:
    %active.lane.mask.entry = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 %N)
    %N_minus_VF = select %N > 16 ? %N - 16 : 0

  vector.body:
    %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
    %active.lane.mask = phi <vscale x 16 x i1> [ %active.lane.mask.entry, %vector.ph ], [ %active.lane.mask.next, %vector.body ]
    ...

    %active.lane.mask.next = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 %index, i64 %N_minus_VF)
    %index.next = add i64 %index, %4
      ; The add above may still overflow, but this time the active.lane.mask is not affected
    %8 = extractelement <vscale x 16 x i1> %active.lane.mask.next, i64 0
    br i1 %8, label %vector.body, label %for.cond.cleanup, !llvm.loop !7

For N = 20, we'd then get:

  vector.ph:
    %active.lane.mask.entry = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 %N)
      ; %active.lane.mask.entry = <1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1>
    %N_minus_VF = select 20 > 16 ? 20 - 16 : 0
      ; %N_minus_VF = 4

  vector.body: (1st iteration)
    ... ; using <1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1> as predicate in the loop
    ...
    %active.lane.mask.next = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 4)
      ; %active.lane.mask.next = <1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0>
    %index.next = add i64 0, 16
      ; %index.next = 16
    %8 = extractelement <vscale x 16 x i1> %active.lane.mask.next, i64 0
      ; %8 = 1
    br i1 %8, label %vector.body, label %for.cond.cleanup, !llvm.loop !7
      ; branch to %vector.body

  vector.body: (2nd iteration)
    ... ; using <1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0> as predicate in the loop
    ...
    %active.lane.mask.next = tail call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 16, i64 4)
      ; %active.lane.mask.next = <0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0>
    %index.next = add i64 16, 16
      ; %index.next = 32
    %8 = extractelement <vscale x 16 x i1> %active.lane.mask.next, i64 0
      ; %8 = 0
    br i1 %8, label %vector.body, label %for.cond.cleanup, !llvm.loop !7
      ; branch to %for.cond.cleanup

Reviewed By: fhahn, david-arm

Differential Revision: https://reviews.llvm.org/D142109
2023-03-01 09:01:19 +00:00
Sander de Smalen
de111ae70a NFC: Use generate_test_checks script for LV tests which seem to have been auto-generated. 2023-03-01 09:01:19 +00:00
Sander de Smalen
0d94b63604 [IR] Add LLVM IR support for target("aarch64.svcount") type.
The C and C++ Language Extensions for AArch64 SME2 [1] adds a new type called
`svcount_t` which describes a predicate. This is not a predicate vector
mask, but rather a description of a predicate vector mask that can be
expanded into a mask using explicit instructions. The type is a scalable
opaque type.

To implement `svcount_t` type this patch uses the existing Target Extension Type
mechanism, but adds further support so that this type can be a scalable type.

AArch64 CodeGen support will follow in a separate patch.

[1] https://github.com/ARM-software/acle/pull/217

Reviewed By: jcranmer-intel, nikic

Differential Revision: https://reviews.llvm.org/D136861
2023-03-01 08:17:53 +00:00
Ting Wang
65f68812d3 [PowerPC] update PPCTTIImpl::supportsTailCallFor() check conditions
This patch reuse `PPCTargetLowering::isEligibleForTCO()` to check
`PPCTTIImpl::supportsTailCallFor()`.

Fixes #59315

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D140369
2023-02-28 22:29:16 -05:00
Kazu Hirata
368c9f8813 Revert "[ControlHeightReduction] Don't combine a "poison" branch"
This reverts commit 38a64aab4a3fbaaeb383638ff654247902796556.

llvm-clang-x86_64-expensive-checks-debian is failing:

https://lab.llvm.org/buildbot/#/builders/16/builds/44249
2023-02-28 17:58:45 -08:00
Kazu Hirata
38a64aab4a [ControlHeightReduction] Don't combine a "poison" branch
Without this patch, the control height reduction pass would combine a
"poison" branch with an earlier well-defined branch, turning the
earlier branch into a "poison" branch also.

This patch fixes the problem by rejecting "poison" conditional
branches.

Differential Revision: https://reviews.llvm.org/D145008
2023-02-28 16:13:30 -08:00
Sanjay Patel
542e70f96c [InstCombine] reassociate subtract-from-constant to add-constant
(C - X) + Y --> (Y - X) + C

Moving the constant operand to an 'add' gives more
flexibility to subsequent reassociation patterns,
and it may be better for codegen on targets that
don't have subtract-from-immediate instructions.
2023-02-28 14:21:13 -05:00
Yaxun (Sam) Liu
fbec8f04ab [SimplifyCFG] Do not hoist/sink convergent function calls
Currently SimplifyCFG hoists/sink common instructions in then/else basic blocks
when certain options are enabled, which is the case for default clang optimization
pipelines for -O3. It tries to hoist/sink convergent function calls in divergent
control flow, which causes incorrect ISA generated for GPU, e.g.
https://github.com/ROCm-Developer-Tools/HIP/issues/3172

This patch fixes that by conservatively disable hoisting/sinking common
convergent function calls in then/else blocks.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D144756
2023-02-28 12:41:56 -05:00
Alexey Bataev
1d6b5b66bb [SLP]Fix PR61050: Assertion `I->use_empty() && "trying to erase instruction with users."
When gathering the counter for the reused scalars, need to use reduced
value, not the original reduced value. Same values counter is gathered
for reduced values, not original ones.
2023-02-28 07:51:34 -08:00
Sanjay Patel
3b090ff2bd [InstCombine] use demanded vector elements to eliminate partially redundant instructions
In issue #60632, we have vector math ops that differ because an
operand is shuffled, but the math has limited demanded elements,
so it can be replaced by another instruction:
https://alive2.llvm.org/ce/z/TKqq7H

I don't think we have anything like this yet - it's like a
CSE/GVN fold, but driven by demanded elements of a vector op.
This is limited to splat-0 as a first step to keep it simple.

Differential Revision: https://reviews.llvm.org/D144760
2023-02-28 09:43:44 -05:00
sgokhale
ac67ec3a54 [LV] Reland testcase in 0ec4cae 2023-02-28 18:14:18 +05:30
sgokhale
0ec4cae146 [LV] Modify test case for commit 4f9a544
Was observing test failure. Relanding the test
2023-02-28 18:07:36 +05:30
sgokhale
4f9a5447c6 [LV] Reland "Update logic for calculating register usage due to invariants"
Previously, while calculating register usage due to invariants, it was assumed that invariant would always be part of widening
instructions. This resulted in calculating vector register types for vectors which cant be legalized(check the newly added test for more details).

An invariant might not always need a vector register. For e.g., invariant might just be used for iteration check.

This patch checks if the invariant is part of any widening instruction and considers register usage accordingly. Fixes issue 60493

Differential Revision: https://reviews.llvm.org/D143422
2023-02-28 17:32:39 +05:30
Florian Hahn
c34936465c
[GlobalOpt] Split CleanupPointerRootUsers test with constant exprs.
Split tests for D144468. Adding a test with an icmp constant expression
stopped CleanupPointerRootUsers from being called. Move it to a
separate test.
2023-02-28 11:40:37 +01:00
sgokhale
3c8ddbde37 Revert "[LV] Update logic for calculating register usage due to invariants"
Observing test failure for llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll

This reverts commit d1628266946fdddb44bdad2b3ccf3cd5fc769f42.
2023-02-28 15:46:59 +05:30
luxufan
207854b07d [Local][InstCombine] Handle MD_noundef in combineMetadataCSE
Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D144942
2023-02-28 18:09:04 +08:00
Dmitry Makogon
4e34915b6d [GuardWidening] Make sure widened condition operands are available at insertion point
This fixes a possible issue when we could hoist an instruction up to a widenable
condition intrinsic call without making sure its operands are available at
hoisiting point.

Recently insertion point finding algorithm changed a bit, so this availability
check became necessary.

Verifier would crash after we handled the following special case:
  L >u C0 && L >u C1  ->  L >u max(C0, C1),
Previously we would insert the new condition right before the widenable condition
branch where all L operands were available.
Now we may choose the widenable condition intrinsic call as insertion point and it may
happen so that the L operands are computed after the call, so we have to make sure that
L operands are available at the point we want to insert it.

Differential Revision: https://reviews.llvm.org/D144944
2023-02-28 16:30:09 +07:00
Dmitry Makogon
10cee82120 [Test] Add test exposing hoisting bug in GuardWidening (NFC)
It hoits instruction without making sure its operands are
available at hoisiting point.
2023-02-28 15:08:32 +07:00
Jun Zhang
f88436c3f3
[InstCombine] Fold signbit test of a pow2 or zero
(X & X) <  0 --> X == MinSignedC
(X & X) > -1 --> X != MinSignedC

Alive2: https://alive2.llvm.org/ce/z/_J5q3S
Closes: https://github.com/llvm/llvm-project/issues/60957

Signed-off-by: Jun Zhang <jun@junz.org>

Differential Revision: https://reviews.llvm.org/D144777
2023-02-28 15:52:13 +08:00
sgokhale
d162826694 [LV] Update logic for calculating register usage due to invariants
Previously, while calculating register usage due to invariants, it was assumed that invariant would always be part of widening
instructions. This resulted in calculating vector register types for vectors which cant be legalized(check the newly added test for more details).

An invariant might not always need a vector register. For e.g., invariant might just be used for iteration check.

This patch checks if the invariant is part of any widening instruction and considers register usage accordingly. Fixes issue 60493

Differential Revision: https://reviews.llvm.org/D143422
2023-02-28 11:05:26 +05:30
Arthur Eubanks
45391e1394 [test] Remove unnecessary -enable-new-pm=0 2023-02-27 14:17:24 -08:00
Matthew Voss
4364e2429c [NFC][PGO] Prefix duplicate profile MemOp entry diagnostic with 'warning:'
Adding this prefix will indicate clearly that the compiler doesn't exit
when it hits this diagnostic. Searches for other non-fatal diagnostics
will also be able to find this diagnostic easily.
2023-02-27 14:04:27 -08:00
Vasileios Porpodas
a700fb3d9b [SLP] Fixes crash in BoUpSLP::isGatherShuffledEntry()
Crash caused by: 708eb1b96d9a36f9c0182b7d53c492059778fa35

Differential Revision: https://reviews.llvm.org/D144895
2023-02-27 12:29:25 -08:00
Alexey Bataev
007177bdde [SLP]Fix PR61018: Assertion `Mask[I] == UndefMaskElem && "Multiple uses
of scalars."' failed.

Need to check for the reused indices when checking if 2 insertelement
instruction are from the same buildvector. If the inidices are reused,
better not to match buildvectors and consider them as differenet,
otherwise need to track the order of insertelement operations.
2023-02-27 10:09:48 -08:00
Nikita Popov
5d6dfba1a8 [ConstExpr] Avoid creation of select constant expressions
These expressions will now only be created if explicitly requested
in IR/bitcode (and by LowerTypeTests, which has a tricky to remove
use).

This is in preparation for removing these expressions entirely,
but also fixes #60983 in the meantime.
2023-02-27 17:10:05 +01:00
Alexey Bataev
5f53e85f8a [SLP]Fix a crash when trying to find reduced ops for the reduced value.
Need to use original reduced value, not the one the compiler gets after
reduction, it may be replaced by the extractelement instruction already.
2023-02-27 07:32:36 -08:00
Nikita Popov
49aa3777f8 [GlobalOpt] Ignore only loaded / only stored global parts in global SRA heuristic
When limiting the number of parts we split a global into, ignore
any parts that are either only loaded or only stored, because we
expect these to be optimized away after SRA.

Differential Revision: https://reviews.llvm.org/D129857
2023-02-27 14:58:08 +01:00
Max Kazantsev
a18ce47a3e [LoopPredication] Account for critical edges when inserting assumes. PR26496
Loop predication can insert assumes to preserve knowledge about some facts that
may otherwise be lost, because loop predication is a lossy transform. When a guard
is represented as branch by widenable condition, it should insert it in the guarded
block. However, if the guarded block has other predecessors than the guard block,
then the condition might not dominate it. Currently we generate invalid code here.

One possible fix here is to split critical edge and insert the assume there, but in
this case we should modify CFG, which Loop Predication is not currently doing, and we
want to keep it that way.

The fix is to handle this case by inserting a Phi which takes `Cond` as input from the
guard block and `true` from any other blocks. This is valid in terms of IR and does
not introduce any new knowledge if we came from another block.

Differential Revision: https://reviews.llvm.org/D144859
Reviewed By: nikic, skatkov
2023-02-27 18:26:17 +07:00
Nikita Popov
ee2f9d6dfb Reapply [InstCombine] Remove early constant fold
The reported compile-time regression has been address in
47f9109dff80a1abbe2705ee71dc0882b1d62274.

Additionally, this contains a change to immediately fold zext
with constant operand, even if it's used in a trunc. I'm not sure
if this is relevant for anything, but I noticed it as a behavioral
discrepancy when investigating this issue.

-----

InstCombine currently performs a constant folding attempt as part
of the main InstCombine loop, before visiting the instruction.
However, each visit method will also attempt to simplify the
instruction, which will in turn constant fold it. (Additionally,
we also constant fold instructions before the main InstCombine loop
and use a constant folding IR builder, so this is doubly redundant.)

There is one place where InstCombine visit methods currently don't
call into simplification, and that's casts. To be conservative,
I've added an explicit constant folding call there (though it has
no impact on tests).

This makes for a mild compile-time improvement and in particular
mitigates the compile-time regression from enabling load
simplification in be88b5814d9efce131dbc0c8e288907e2e6c89be.

Differential Revision: https://reviews.llvm.org/D144369
2023-02-27 12:23:06 +01:00
Max Kazantsev
3bfb2357f7 [Test] Add failing test for PR61022
Details: https://github.com/llvm/llvm-project/issues/61022
2023-02-27 17:20:01 +07:00
Sergey Kachkov
1aece0e5ed Revert "[GVN] Support address translation through select instructions"
This reverts commit b5bf6f6392a3408be1b7b7e036eb69358c5a2c29.
2023-02-27 12:57:59 +03:00
Sergey Kachkov
b5bf6f6392 [GVN] Support address translation through select instructions
Process cases when phi incoming in predecessor block has select
instruction, and this select address is unavailable, but there
are addresses translated from both sides of select instruction.

Differential Revision: https://reviews.llvm.org/D142705
2023-02-27 12:08:15 +03:00
Jun Zhang
cf491a165f
Precommit test for D144777, NFC
Signed-off-by: Jun Zhang <jun@junz.org>
2023-02-27 12:23:18 +08:00
William S. Moses
58eac856cc [LICM] Ensure LICM can hoist invariant.group
Invariant.group's are not sufficiently handled by LICM. Specifically,
if a given invariant.group loaded pointer is not overwritten between
the start of a loop, and its use in the load, it can be hoisted.
The invariant.group (on an already invariant pointer operand) ensures
the result is the same. If it is not overwritten between the start
of the loop and the load, it is therefore legal to hoist.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D144053
2023-02-26 12:41:41 -05:00
zhongyunde
74ad19c25d [MergeICmps] Adapt to non-eq comparisons, retry
Fix https://github.com/llvm/llvm-project/issues/59740.
NOTE: retry as we can't reproduce the break locally when first commit.

Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D141188
2023-02-27 01:26:13 +08:00