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11 Commits

Author SHA1 Message Date
serge-sans-paille
989f1c72e0 Cleanup codegen includes 
This is a (fixed) recommit of https://reviews.llvm.org/D121169

after:  1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681
 2022-03-16 08:43:00 +01:00
Nico Weber
a278250b0f Revert "Cleanup codegen includes" 
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https://reviews.llvm.org/D121169
 2022-03-10 07:59:22 -05:00
serge-sans-paille
7f230feeea Cleanup codegen includes 
after:  1061034926
before: 1063332844

Differential Revision: https://reviews.llvm.org/D121169
 2022-03-10 10:00:30 +01:00
Sebastian Neubauer
bf980930e5 [AMDGPU] Ignore KILLs when forming clauses 
KILL instructions are sometimes present and prevented hard
clauses from being formed.

Fix this by ignoring all meta instructions in clauses.

Differential Revision: https://reviews.llvm.org/D106042
 2021-09-27 16:33:52 +02:00
Carl Ritson
9cf6ff7aff [AMDGPU] Do not clause NSA instructions 
To ensure correct behaviour NSA instructions should not be claused.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D102211
 2021-05-14 12:54:56 +09:00
Jay Foad
9e026273b0 [AMDGPU] SIInsertHardClauses: move more stuff into the class. NFC. 2021-05-06 14:47:54 +01:00
dfukalov
560d7e0411 [NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargets 
... to reduce headers dependency.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D95036
 2021-01-20 22:22:45 +03:00
dfukalov
6a87e9b08b [NFC][AMDGPU] Reduce include files dependency. 
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D93813
 2021-01-07 22:22:05 +03:00
hsmahesha
0ed2c04636 [AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes 
Summary:
While clustering mem ops, AMDGPU target needs to consider number of clustered bytes
to decide on max number of mem ops that can be clustered. This patch adds support to pass
number of clustered bytes to target mem ops clustering logic.

Reviewers: foad, rampitec, arsenm, vpykhtin, javedabsar

Reviewed By: foad

Subscribers: MatzeB, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, javed.absar, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80545
 2020-06-01 22:52:34 +05:30
Jay Foad
10c10f2419 [AMDGPU] Fix assertion failure in SIInsertHardClauses 
This new pass failed an assertion whenever there were s_nops after the
end of clause.

Differential Revision: https://reviews.llvm.org/D80007
 2020-05-15 15:49:52 +01:00
Jay Foad
42a5560503 [AMDGPU] New SIInsertHardClauses pass 
Enable clausing of memory loads on gfx10 by adding a new pass to insert
the s_clause instructions that mark the start of each hard clause.

Differential Revision: https://reviews.llvm.org/D79792
 2020-05-14 18:54:49 +01:00