This patch fixes issue with the LU32I_D instruction, which did not have
an input register operand.
Differential Revision: https://reviews.llvm.org/D122970
This patch constructs codegen infra and successfully generate the first
'add' instruction. Add integer calling convention for fixed arguments which
are passed with general-purpose registers.
New test added here:
CodeGen/LoongArch/ir-instruction/add.ll
The test file is placed in a subdirectory because we will use
subdirctories to distinguish different categories of tests (e.g.
intrinsic, inline-asm ...)
Reviewed By: MaskRay, SixWeining
Differential Revision: https://reviews.llvm.org/D122366
All LLVM backends use MCDisassembler as a base class for their
instruction decoders. Use "const MCDisassembler *" for the decoder
instead of "const void *". Remove unnecessary static casts.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D122245
With the addition of disassembler now we can do instructions 'round-trip' test
that assembles `.s` to obj with `llvm-mc` and disassembles it with `llvm-objdump`
to check instruction mnemonics.
Reviewed By: xen0n, MaskRay
Differential Revision: https://reviews.llvm.org/D120477
This patch adds basic support to AsmParser which can handle basic
instructions with register or immediate operands. With the addition of
the parser, now it's possible to test instructions encoding with `llvm-mc`.
Disassembler will be added later and then we can do `round-trip` test.
Reviewed By: xen0n, MaskRay, myhsu
Differential Revision: https://reviews.llvm.org/D120476
This is a split patch of D120476 and thanks to myhsu.
'Transformed' means the encoding of an immediate is not the same as
its binary representation. For example, the `bl` instruction
requires a signed 28-bits integer as its operand and the low 2 bits
must be 0. So only the upper 26 bits are needed to get encoded into
the instruction.
Based on the above reason this kind of immediate needs a customed
`EncoderMethod` to get the real value getting encoded into the
instruction.
Currently these immediate includes:
```
uimm2_plus1
simm14_lsl2
simm16_lsl2
simm21_lsl2
simm26_lsl2
```
This patch adds those `EncoderMethod`s and revises related .mir test
in previous patch.
Reviewed By: xen0n, MaskRay
Differential Revision: https://reviews.llvm.org/D120545
This patch corrects some instruction definitions that I incorrectly wrote
in initial patches including bstr{ins/pick}.{w/d}, ll.{w/d} and sc.{w/d}.
Reviewed By: xen0n
Differential Revision: https://reviews.llvm.org/D119817
This patch adds a '$' prefix to register name in InstPrinter that I missed in initial patches.
Reviewed By: xen0n
Differential Revision: https://reviews.llvm.org/D119813
This patch introduces basic tablegen infra such as
LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td.
For now, only add instruction definitions for LoongArch basic integer
operations.
Our initial target is a working MC layer rather than codegen,
so appropriate SelectionDAG patterns will come later.
Differential revision: https://reviews.llvm.org/D115861
This patch registers the 'loongarch32' and 'loongarch64' targets. Also adds a
simple testcase to check the output of llc --vesion containing the targets.
Differential revision: https://reviews.llvm.org/D115860
