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Author	SHA1	Message	Date
alex-t	a0ea7ec90f	[AMDGPU] divergence patterns for the BUILD_VECTOR i16, undef expansion. BUILD_VECTOR of i16 and undef gets expanded to the COPY_TO_REGCLASS. The latter is further lowererd to the copy instructions. We need to provide the correct register class for the uniform and divergent BUILD_VECTOR nodes to avoid VGPR to SGPR copies. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D122068	2022-03-21 21:11:20 +01:00
Jay Foad	aa1e5fbc9b	[AMDGPU] Fix permissions on test files	2022-02-24 12:17:54 +00:00
alex-t	e4103c91f8	[AMDGPU] Select build_vector DAG nodes according to the divergence This change enables divergence-driven instruction selection for the build_vector DAG nodes. It also enables packed i16 instructions for GFX9. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D116187	2021-12-23 02:27:12 +03:00

Author

SHA1

Message

Date

alex-t

a0ea7ec90f

[AMDGPU] divergence patterns for the BUILD_VECTOR i16, undef expansion.

BUILD_VECTOR of i16 and undef gets expanded to the COPY_TO_REGCLASS.
         The latter is further lowererd to the copy instructions.
	 We need to provide the correct register class for the uniform and divergent BUILD_VECTOR nodes
	 to avoid VGPR to SGPR copies.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D122068

2022-03-21 21:11:20 +01:00

Jay Foad

aa1e5fbc9b

[AMDGPU] Fix permissions on test files

2022-02-24 12:17:54 +00:00

alex-t

e4103c91f8

[AMDGPU] Select build_vector DAG nodes according to the divergence

This change enables divergence-driven instruction selection for the build_vector DAG nodes.
It also enables packed i16 instructions for GFX9.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D116187

2021-12-23 02:27:12 +03:00

3 Commits