7 Commits

Author SHA1 Message Date
Jay Foad
c246b7bd4a [AMDGPU] Only count global-to-global as indirect accesses
Previously any load (global, local or constant) feeding into a
global load or store would be counted as an indirect access. This
patch only counts global loads feeding into a global load or store.
The rationale is that the latency for global loads is generally
much larger than the other kinds.

As a side effect this makes it easier to write small kernels test
cases that are not counted as having indirect accesses, despite
the fact that arguments to the kernel are accessed with an SMEM
load.

Differential Revision: https://reviews.llvm.org/D122804
2022-04-01 13:48:13 +01:00
Jay Foad
fdaf606c8e [AMDGPU] Fix last remaining checks in perfhint.ll
Unfortunately this just shows that the test case for D47740 never
really tested what it was supposed to test.

Differential Revision: https://reviews.llvm.org/D122664
2022-03-31 13:39:15 +01:00
Stanislav Mekhanoshin
a397c1c82f [AMDGPU] Tune perfhint analysis to account access width
A function with less memory instructions but wider access
is the same as a function with more but narrower accesses
in terms of memory boundness. In fact the pass would give
different answers before and after vectorization without
this change.

Differential Revision: https://reviews.llvm.org/D105651
2021-07-21 12:46:10 -07:00
Jay Foad
f05bce86af [AMDGPU] Add some missing check prefixes and tweak test
The test needed some extra ALU instructions to prevent it from being
memory bound.
2020-07-17 12:57:47 +01:00
Jay Foad
2dc3d1b313 [AMDGPU] Add some missing check prefixes 2020-07-17 12:56:29 +01:00
Stanislav Mekhanoshin
7ba3fc730c [AMDGPU] Do not consider indirect acces through phi for wave limiter
Rational: if there is indirect access that is usually an issue
because load is not ready by the use. However, if use is inside a
loop and load is outside that is potentially an issue for a first
iteration only.

Differential Revision: https://reviews.llvm.org/D47740

llvm-svn: 334420
2018-06-11 16:50:49 +00:00
Stanislav Mekhanoshin
1c538423dc [AMDGPU] Add perf hints to functions
This is adoption of HSAIL perfhint pass. Two types of hints are produced:

1. Function is memory bound.
2. Kernel can use wave limiter.

Currently these hints are used in the scheduler. If a function is suspected
to be memory bound we allow occupancy to decrease to 4 waves in the course
of scheduling.

Differential Revision: https://reviews.llvm.org/D46992

llvm-svn: 333289
2018-05-25 17:25:12 +00:00