3 Commits

Author	SHA1	Message	Date
Nick Desaulniers	79ebc3b0dd	[llvm][test] rewrite callbr to use i rather than X constraint NFC ... In D115311, we're looking to modify clang to emit i constraints rather than X constraints for callbr's indirect destinations. Prior to doing so, update all of the existing tests in llvm/ to match. Reviewed By: void, jyknight Differential Revision: https://reviews.llvm.org/D115410	2022-01-11 11:31:08 -08:00
Nick Desaulniers	9c4b49db19	[ShrinkWrap] check for PPC's non-callee-saved LR ... As pointed out in https://reviews.llvm.org/D115688#inline-1108193, we don't want to sink the save point past an INLINEASM_BR, otherwise prologepilog may incorrectly sink a prolog past the MBB containing an INLINEASM_BR and into the wrong MBB. ShrinkWrap is getting this wrong because LR is not in the list of callee saved registers. Specifically, ShrinkWrap::useOrDefCSROrFI calls RegisterClassInfo::getLastCalleeSavedAlias which reads CalleeSavedAliases which was populated by RegisterClassInfo::runOnMachineFunction by iterating the list of MCPhysReg returned from MachineRegisterInfo::getCalleeSavedRegs. Because PPC's LR is non-allocatable, it's NOT considered callee saved. Add an interface to TargetRegisterInfo for such a case and use it in Shrinkwrap to ensure we don't sink a prolog past an INLINEASM or INLINEASM_BR that clobbers LR. Reviewed By: jyknight, efriedma, nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D116424	2022-01-11 10:01:34 -08:00
Stefan Pintilie	15051f0b4a	[PowerPC] Handle inline assembly clobber of link regsiter ... This patch adds the handling of clobbers of the link register LR for inline assembly. This patch is to fix: https://bugs.llvm.org/show_bug.cgi?id=50147 Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D101657	2021-05-13 07:43:37 -05:00