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3 Commits

Author SHA1 Message Date
Nemanja Ivanovic
766ca2c59e [PowerPC] Add missed VSX shuffles instead of Altivec ones 
VSX introduced some permute instructions that are direct
replacements for Altivec ones except they can target all
the VSX registers. We have added code generation for most
of these but somehow missed the low/hi word merges (XXMRG[LH]W).
This caused some additional spills on some large
computationally intensive code.

This patch simply adds the missed patterns.
 2022-03-14 10:11:54 -05:00
QingShan Zhang
8b6674e64f [NFC][Test] Update the test with update_llc_test_checks.py 2020-10-09 02:26:03 +00:00
Roland Froese
b6d7ed469f [PowerPC] Extend custom lower of vector truncate to handle wider input 
Current custom lowering of truncate vector handles a source of up to 128 bits, but that only uses one of the two shuffle vector operands. Extend it to use both operands to handle 256 bit sources.

Differential Revision: https://reviews.llvm.org/D68035
 2020-08-24 15:33:43 -04:00