4 Commits

Author	SHA1	Message	Date
Fraser Cormack	e9ceeedf30	[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests	2022-02-01 11:06:56 +00:00
eopXD	3cf15af2da	[RISCV] Remove experimental prefix from rvv-related extensions. ... Extensions affected: +v, +zve*, +zvl* Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D117860	2022-01-22 20:18:40 -08:00
wangpc	af0ecfccae	[RISCV] Generate pseudo instruction li ... Add an alias of `addi [x], zero, imm` to generate pseudo instruction li, which makes assembly mush more readable. For existed tests, users can update them by running script `llvm/utils/update_llc_test_checks.py`. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D112692	2021-11-22 14:01:37 +08:00
Craig Topper	ce7b8343be	[RISCV] Merge vector tests for rv32 and rv64 into a single test file ... These tests have nearly identical content the only difference is that the rv64 test has a signext attribute on some parameters. That attribute should be harmless on rv32. Merge them into a single test file with 2 RUN lines. Differential Revision: https://reviews.llvm.org/D112242	2021-10-22 09:04:30 -07:00