4 Commits

Author SHA1 Message Date
Guozhi Wei
6599961c17 [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
This patch contains following enhancements to SrcRegMap and DstRegMap:

  1 In findOnlyInterestingUse not only check if the Reg is two address usage,
    but also check after commutation can it be two address usage.

  2 If a physical register is clobbered, remove SrcRegMap entries that are
    mapped to it.

  3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
    entry only when the COPY instruction is coalescable. (The COPY src is
    killed)

With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.

Differential Revision: https://reviews.llvm.org/D108731
2021-10-11 15:28:31 -07:00
Simon Pilgrim
350ab7aa1c [DAG] Simplify OR(X,SHL(Y,BW/2)) eq/ne 0/-1 'all/any-of' style patterns
Attempt to simplify all/any-of style patterns that concatenate 2 smaller integers together into an and(x,y)/or(x,y) + icmp 0/-1 instead.

This is mainly to help some bool predicate reduction patterns where we end up concatenating bool vectors that have been bitcasted to integers.

Differential Revision: https://reviews.llvm.org/D93599
2021-01-07 12:03:19 +00:00
Simon Pilgrim
3f8c2520c0 [X86] Add commuted patterns test coverage for D93599
Suggested by @spatel
2021-01-06 18:03:20 +00:00
Simon Pilgrim
dfcb872c3e [X86] Add scalar/vector test coverage for D93599
This expands the test coverage beyond just the boolvector/movmsk concat pattern
2021-01-06 11:58:27 +00:00