228029 Commits

Author SHA1 Message Date
Fangrui Song
c161b30f5c [yaml2obj] Support R_PPC_* relocation types 2022-02-04 15:11:50 -08:00
Róbert Ágoston
cd4ed08b5a [GlobalISel] Don't combine instructions which are fed by memory instructions using different size
Memory instructions like extending loads from the same address are not equal if
their size is not equal.

This fixes https://github.com/llvm/llvm-project/issues/53524.

Differential Revision: https://reviews.llvm.org/D118805
2022-02-04 15:00:47 -08:00
Joseph Huber
6b78526b1b [OpenMP] Emit remark on the captured call instead of the variable
Changes the remark to emit on the function call that captures the globalized
variable instead of the globalized variable itself. The user should be able to
see which variable it was in the argument list of the function.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106980
2022-02-04 17:50:53 -05:00
Matt Arsenault
8b8b491379 AMDGPU/GlobalISel: Fix assertions on invalid addrspacecasts
Fixes some assert on invalid situations and starts directly emitting
the error.
2022-02-04 17:28:49 -05:00
Matt Arsenault
f1f15d0285 AMDGPU: Fix failing test 2022-02-04 16:54:09 -05:00
Masoud Ataei
8ce13bc93b [PowerPC] Option controling scalar MASS convertion
differential: https://reviews.llvm.org/D119035

reviewer: bmahjour
2022-02-04 13:24:22 -08:00
Paulo Matos
c67c9cfe3f [WebAssembly] Refactor and fix emission of external IR global decls
Reland of 00bf4755.

This patches fixes the visibility and linkage information of symbols
referring to IR globals.

Emission of external declarations is now done in the first execution
of emitConstantPool rather than in emitLinkage (and a few other
places). This is the point where we have already gathered information
about used symbols (by running the MC Lower PrePass) and not yet
started emitting any functions so that any declarations that need to
be emitted are done so at the top of the file before any functions.

This changes the order of a few directives in the final asm file which
required an update to a few tests.

Reviewed By: sbc100

Differential Revision: https://reviews.llvm.org/D118995
2022-02-04 22:01:46 +01:00
Matt Arsenault
4622afa94c AMDGPU: Convert AMDGPUResourceUsageAnalysis to a Module pass
This is more precise in the face of indirect calls and aliases, still
assuming the call target is defined somewhere in the current module.

This sometimes changes the order the functions are printed, and also
changes the point where context errors are printed relative to
stdout. This also likely has negative consequences for compile time
and memory usage.
2022-02-04 15:56:04 -05:00
Matt Arsenault
935abab65c AMDGPU: Use module level register maximums for unknown callees
Compute the theoretical register budget based on the IR function
signature/attributes, and use the global maximum register budgets for
unknown callees.

This should fix the kernel reported register usage in the presence of
indirect calls. The previous fix in
2b08f6af62afbf32e89a6a392dbafa92c62f7bdf was incorrect becauset it was
only taking the maximum in the known call graph, and missing something
that was either outside of it or codegened later.

This fixes a second case I discovered where calls to aliases also did
not work as expected. CallGraphAnalysis misses these, so functions
called through aliases were not codegened ahead of callers as
expected. CallGraphAnalysis should probably be fixed to understand
this case, and there's likely a bug with IPRA here. This fixes
numerous failures in the conformance test at -O0.
2022-02-04 15:56:03 -05:00
Arthur Eubanks
69873633bd [gn build] Port dbed14d 2022-02-04 12:52:33 -08:00
minglotus-6
d70bd7a148 Clean up a test case.
The test case is added to demonstrate diff before and after patch D114832.

The solution is

Differential Revision: https://reviews.llvm.org/D118846
2022-02-04 12:49:13 -08:00
Simon Pilgrim
78c6b90000 [APInt] Update APInt::isShiftedMask() description. NFC.
Make it clear that it matches a non-empty sequence of ones, matches the descriptions for isShiftedMask_32/64 as suggested on D119019
2022-02-04 20:39:05 +00:00
Florian Mayer
02dbed4b7f [mte] [nfc] do not keep Tag in AllocaInfo
this is to get the implementation closer to HWASan

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D118960
2022-02-04 12:34:22 -08:00
Philip Reames
0cc6165d05 [SLP] Strengthen internal asserts about scheduled node state [NFC]
All members of a scheduled bundle must have valid dependencies, with no unscheduled ones, and only the lead element gets marked scheduled.
2022-02-04 12:22:52 -08:00
Sanjay Patel
fff3e1dbaa [x86] enable fast sqrtss/sqrtps tuning for AMD Zen cores
As discussed in D118534, all of the recent AMD CPUs have
relatively fast (<14 cycle latency) "sqrtss" and "sqrtps"
instructions:
https://uops.info/table.html?search=sqrtps&cb_lat=on&cb_tp=on&cb_SNB=on&cb_SKL=on&cb_ZENp=on&cb_ZEN2=on&cb_ZEN3=on&cb_measurements=on&cb_avx=on&cb_sse=on

So we should set this tuning flag to alter codegen of plain
"sqrt(X)" expansion (as opposed to reciprocal-sqrt - there
is other test coverage for that pattern). The expansion is
both slower and less accurate than the hardware instruction.

Differential Revision: https://reviews.llvm.org/D119001
2022-02-04 13:59:20 -05:00
Keith Smiley
dbed14d215 [llvm-libtool-darwin] Fix crash with bitcode asm module
When using llvm-libtool-darwin with LTO building llvm itself, it crashed
on a file with an asm module in the bitcode. This fixes that by
correctly registering the targets for this.

Differential Revision: https://reviews.llvm.org/D118575
2022-02-04 10:54:27 -08:00
LLVM GN Syncbot
e55ace6c37 [gn build] Port 1d8bbe3d255f 2022-02-04 18:44:32 +00:00
Craig Topper
1d8bbe3d25 [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
Using AArch64's original implementation for reference, this patch
implements a pass to remove unneeded copies of X0. This pass runs
after register allocation and looks to see if a register is implied
to be 0 by a branch in the predecessor basic block.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118160
2022-02-04 10:43:46 -08:00
Florian Mayer
3918dd6b8a [mte] fix runOnFunction return value falsely suggesting function was modified.
If NumInterestingAllocas == 0 we do not add any instrumentation or
padding in the previous loop.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D118961
2022-02-04 10:34:14 -08:00
Philip Reames
f3f8e3da9f [SLP] Remove ScheduleData::UnscheduledDepsInBundle field [NFC-ish]
We can simply compute the value of this field on demand.  Doing so clarifies the behavior when one of the instructions within a bundle doesn't have valid dependencies.  I vaguely thing this could change behavior slightly, but none of the test cases are affected, and my attempts to write one by hand have failed.

This also minorly reduces memory usage, but that's a secondary value at best.
2022-02-04 10:12:09 -08:00
LLVM GN Syncbot
6dbba770a8 [gn build] Port 4a02562275d4 2022-02-04 17:43:11 +00:00
LLVM GN Syncbot
8b84ed23d9 [gn build] Port 44cdca37c01a 2022-02-04 17:43:10 +00:00
Sebastian Neubauer
4a02562275 [AMDGPU] Lazily init pal metadata on first function
Delay reading global metadata until the first function or the end of
the file is emitted. That way, earlier module passes can set metadata
that is emitted in the ELF.

`emitStartOfAsmFile` gets called when the passes are initialized,
which prevented earlier passes from changing the metadata.

This fixes issues encountered after converting
AMDGPUResourceUsageAnalysis to a Module pass in D117504.

Differential Revision: https://reviews.llvm.org/D118492
2022-02-04 18:39:35 +01:00
Roman Lebedev
55cd727c9a
[SimplifyCFG] 'merge compatible invokes': allow PHI nodes in landing pads
... iff the incoming values for the invokes-to-be-merged
are compatible (identical).
2022-02-04 20:26:44 +03:00
Roman Lebedev
0d384e9228
[NFC][SimplifyCFG] Extract IncomingValuesAreCompatible() out of SafeToMergeTerminators() 2022-02-04 20:26:44 +03:00
Roman Lebedev
332d70cd45
[NFC][SimplifyCFG] 'merge compatible invokes': tests w/ PHI's in landingpad 2022-02-04 20:26:44 +03:00
Jay Foad
a456ace9c1 [AMDGPU] SILoadStoreOptimizer: rewrite checkAndPrepareMerge. NFCI.
Separate the function clearly into:
- Checks that can be done on CI and Paired before the loop.
- The loop over all instructions between CI and Paired.
- Checks that must be done on InstsToMove after the loop.

Previously these were mostly done inside the loop in a very
confusing way.

Differential Revision: https://reviews.llvm.org/D118994
2022-02-04 17:17:29 +00:00
Craig Topper
234e54bdd8 [RISCV] Add more types of shuffles isShuffleMaskLegal.
Add the vslidedown and interleave patterns that I recently implemented.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D118952
2022-02-04 09:13:13 -08:00
Craig Topper
c83905a308 [RISCV] Add inline expansion for vector fround.
This avoids a crash for scalable vectors and or scalarization for
fixed vectors.

The algorithm is different enough that I don't think it makes sense
to merge with ceil/floor/trunc. Algorithm is adapted from gcc's X86
SSE2 output.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D117247
2022-02-04 09:12:09 -08:00
Simon Pilgrim
0b989a03b9 [Support] Add isShiftedMask_32/isShiftedMask_64 unit test coverage 2022-02-04 17:07:02 +00:00
Dawid Jurczak
39ceea26c5 [NFC] Move FoldingSetNodeIDRef::ComputeHash and FoldingSetNodeID::ComputeHash definitions to header
Lack of ComputeHash inlining slows down slightly FoldingSetBase::FindNodeOrInsertPos calls.
Inlining makes it faster which matters in particular for FoldingSet users in ASTContext.

Extracted from: https://reviews.llvm.org/D118385

Differential Revision: https://reviews.llvm.org/D118612
2022-02-04 18:03:42 +01:00
Sanjay Patel
0236c57181 [InstCombine] try to fold one-demanded-bit-of-multiply
This is a generalization of the icmp fold in D118061 (and that can be abandoned).
We're looking for a disguised form of "odd * odd must be odd".
Some Alive2 proofs to show correctness:
https://alive2.llvm.org/ce/z/60Y8hz
https://alive2.llvm.org/ce/z/HfAP6R

Differential Revision: https://reviews.llvm.org/D118539
2022-02-04 11:40:54 -05:00
Sanjay Patel
1eb4f88bfe [x86] add test coverage for AMD Ryzen fast sqrt codegen; NFC 2022-02-04 11:40:54 -05:00
Nikita Popov
b8fbffc8b1 [BitstreamReader] Fix incorrect error forwarding
This code clearly intended to forward the error, but instead
returned the non-error result.
2022-02-04 17:31:12 +01:00
Nikita Popov
c00ef03d73 [BitstreamReader] Handle errors more gracefully
Use proper error reporting instead of report_fatal_error().
2022-02-04 17:23:08 +01:00
Nikita Popov
f392e9d264 [BitcodeReader] Resolve error handling todo
If possible, forward the inner error instead of creating a new
one.
2022-02-04 17:14:45 +01:00
Benjamin Kramer
85243124cf Tweak some uses of std::iota to skip initializing the underlying storage. NFCI. 2022-02-04 17:00:50 +01:00
Nico Weber
466c0d0dc7 [gn build] (manually) port e1db505b42f4 (clang-pseudo) 2022-02-04 10:17:02 -05:00
Jay Foad
001cb43159 [AMDGPU] SILoadStoreOptimizer: fewer calls to offsetsCanBeCombined
Only call offsetsCanBeCombined with Modify = true in cases
where it will really do something. NFC.
2022-02-04 14:52:11 +00:00
Dmitry Preobrazhensky
95a52b376a [AMDGPU][GFX9][DOC][NFC] Corrected description of registers available via getreg/setreg
This is to reflect changes introduced by https://reviews.llvm.org/D118860.
2022-02-04 17:55:32 +03:00
Paul Walker
20085df22a [NFC][SVE] Change useSVEForFixedLengthVectorVT to allow unconditional SVE usage for NEON sized vectors.
Previously useSVEForFixedLengthVectorVT only allowed SVE usage when
the target SVE register length was known to be at least 256bit.
This was true even for NEON sized vectors, which was an artificial
restriction imposed during early SVE bring up.  This now changes so
that callers can opt to use SVE for NEON sized vectors regardless
of the SVE register length.

The patch is NFC because for all places where OverrideNEON is used
we now explicitly also check that SVE code generation for larger
than NEON vectors is enabled.  The intent is that over time these
extra checks will either be removed or the lowering disabled if the
SVE usage proves not beneficial.

Differential Revision: https://reviews.llvm.org/D118957
2022-02-04 14:34:35 +00:00
Jay Foad
00bbda07ae [AMDGPU] SILoadStoreOptimizer: simplify class/subclass checks
Also add a comment explaining the difference between class
and subclass. NFCI.
2022-02-04 14:08:04 +00:00
David Green
74d1fe72f4 [AArch64] Expand UADDLV patterns to SADDLV
We already had some patterns for UADDV(UADDLP(x)) -> UADDLV(x), this
simply expands them to the signed instructions by re-using the tablegen
patterns.

Differential Revision: https://reviews.llvm.org/D118133
2022-02-04 14:07:02 +00:00
Roman Lebedev
36df803dfd
[SimplifyCFG] Merge compatible invokes of a landingpad
While nowadays SimplifyCFG knows how to hoist code from then-else blocks,
sink code from unconditional predecessors, and even promote the latter
by tail-merging `ret`/`resume` function terminators, that isn't everything.

While i (& others) have been trying to deal with merging/sinking `unreachable`,
apparently perhaps the more impactful remaining problem is merging the `throw`
calls.

If we start at the `landingpad`, all the predecessors are unwind edges of `invoke`s,
and in some cases some of the `invoke`s are mergeable.
```
/// This is a weird mix of hoisting and sinking. Visually, it goes from:
///          [...]        [...]
///            |            |
///        [invoke0]    [invoke1]
///           / \          / \
///     [cont0] [landingpad] [cont1]
/// to:
///      [...] [...]
///          \ /
///       [invoke]
///          / \
///     [cont] [landingpad]
```

This simplifies the IR/CFG, at the cost of debug info and extra PHI nodes.

Note that we don't require for *all* the `invokes` of the `landingpad`
to be mergeable, they can form more than a single set, we gracefully handle that.

For now, i completely disallowed normal destination, PHI nodes and indirect invokes
but that can be supported.

Out of all the CTMark projects, only 7zip is C++, so there isn't much impact:
https://llvm-compile-time-tracker.com/compare.php?from=ba8eb31bd9542828f6424e15a3014f80f14522c8&to=722fc871c84f14157d45c2159bc9c8c7e2825785&stat=size-total
... but there it currently causes size-total decrease.

Differential Revision: https://reviews.llvm.org/D117805
2022-02-04 17:04:21 +03:00
Florian Hahn
0a781d98fb
[ConstraintElimination] Add initial signed support.
This patch adds initial support for signed conditions. To do so,
ConstraintElimination maintains two separate systems, one with facts
from signed and one for unsigned conditions.

To start with this means information from signed and unsigned conditions
is kept completely separate. When it is safe to do so, information from
signed conditions may be also transferred to the unsigned system and
vice versa. That's left for follow-ups.

In the initial version, de-composition of signed values just handles
constants and otherwise just uses the value, without trying to
decompose the operation. Again this can be extended in follow-up
changes.

The main benefit of this limited signed support is proving >=s 0
pre-conditions added in D118799. But even this initial version also
fixes PR53273.

Depends on D118799.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D118806
2022-02-04 14:02:48 +00:00
Roman Lebedev
6afbf8354b
[NFC][SimplifyCFG] 'merge compatible invokes': test with PHI nodes in unreachable normal destinations 2022-02-04 16:52:09 +03:00
Nikita Popov
f62a400cdf [Statepoint] Determine return type from elementtype attribute
Based on the LangRef change in D117890, this uses the elementtype
attribute rather than the pointer element type to determine the
statepoint callee function type, making statepoints compatible
with opaque pointers.
2022-02-04 14:40:27 +01:00
Nikita Popov
8f8e13056a [Verifier] Require elementtype on gc.statepoint intrinsics
This enforces the requirement specified in D117890.
2022-02-04 14:29:53 +01:00
Jay Foad
33ef8bdf36 [AMDGPU] SILoadStoreOptimizer: simplify optimizeInstsWithSameBaseAddr
Common up all the calls to CI.setMI. NFCI.
2022-02-04 13:25:05 +00:00
Nikita Popov
46f9e45ef0 [Statepoint] Update gc.statepoint calls in tests with elementtype (NFC)
This updates tests for the LangRef change in D117890.
2022-02-04 14:15:41 +01:00