105 Commits

Author SHA1 Message Date
Job Noorman
c39dd7c1db [RISCV][MC] Add support for RV64E
Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570
2023-03-23 12:32:25 +00:00
Job Noorman
d25751779b Bump RV32E version to 2.0
RV32E was recently [ratified](afd613691c) so we should update the version as our MC-layer support is complete.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D144384
2023-03-23 18:12:26 +08:00
Craig Topper
37f3e53c5b [RISCV] Simplify RISCVISAInfo::compareExtension. NFCI
Instead of having a separate single letter and multiletter ranking
use a unified rank that assigns multiletter a larger value than
single letter.

Once we've ranked the extensions, then we compare using these ranks.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D146273
2023-03-20 22:25:11 -07:00
Craig Topper
91b3051ac8 [RISCV] Remove ExtName from RISCVExtensionInfo.
This field is never used in the compiler and was only used in
unit tests added recently.

It's only used as the value in a map where the extension name
is the key. If we need the string we can get it from the key.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146197
2023-03-16 15:20:25 -07:00
Alex Bradbury
cb743dd837 [RISCV] Consistently error for arch strings with trailing _
RISCVISAInfo::parseArchString would sometimes error for arch strings
with a trailing _ and sometimes accept them. This patch makes it
consistently error.

Differential Revision: https://reviews.llvm.org/D145949
2023-03-14 19:12:07 +00:00
Alex Bradbury
b2fad8027a [RISCV][NFC] Small refactor in RISCVISAInfo::parseArchString
Slightly refactor handling of version extraction for the 'baseline' ISA,
to make an upcoming patch easier to review.
2023-03-14 16:37:34 +00:00
Alex Bradbury
e9a03f360f [RISCV] Reject 'g' with explicit version in parseArchString
There is no versioning scheme for the 'g' shorthand for imafd (or in
current ISA specs, imafd_zifencei_zicsr). As such, the only sensible
behaviour to me seems to be to reject a version for it.

Differential Revision: https://reviews.llvm.org/D145954
2023-03-14 12:46:13 +00:00
Alex Bradbury
a159e58c00 Reland [RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString
Prior to this patch, unrecognised z/s/sx/x prefixed extensions were not
ignored when IgnoreUnknown=true.

The first version of this patch, a7313f83b9ca9, incorrectly used
`!isSupportedExtension(Ext)` rather than `!isSupportedExtension(Name)`.
i.e. checked the full substring rather than the split out name, causing
incorrect behaviour when a version is specified. This was fixed and a
new test case addded.

Differential Revision: https://reviews.llvm.org/D145882
2023-03-13 15:19:15 +00:00
Alex Bradbury
7054aa6d6d Revert "[RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString"
This reverts commit a7313f83b9ca904fade446e000550c69e0887cbf.

Causes a buildbot failure.
2023-03-13 11:20:28 +00:00
Alex Bradbury
a7313f83b9 [RISCV] Fix gaps in IgnoreUnknown=true for RISCVISAInfo::parseArchString
Prior to this patch, unrecognised z/s/sx/x prefixed extensions were not
ignored when IgnoreUnknown=true.

Differential Revision: https://reviews.llvm.org/D145882
2023-03-13 10:53:05 +00:00
Craig Topper
de76c016f7 [RISCV] Consistently place single quotes around extension names in error messages.
Some extensions had them, some did not.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D145817
2023-03-10 12:36:37 -08:00
Craig Topper
2800d57e12 [RISCV] Error if F and Zfinx extensions are specified together.
Fixes #61277

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D145809
2023-03-10 11:26:00 -08:00
Craig Topper
90f6a4cc73 [RISCV] Make D extension imply F extension.
I believe this implies relationship is documented in the current
spec but may have been less clear in an older spec.

We used to report an error so I think it should be ok to change this.
Only someone expecting the error should be impacted.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D145125
2023-03-06 19:59:47 -08:00
Alex Bradbury
ff93c9beef [lld][RISCV] Avoid error when encountering unrecognised ISA extensions/versions in RISC-V attributes
This patch follows on from this RFC thread
<https://discourse.llvm.org/t/rfc-resolving-issues-related-to-extension-versioning-in-risc-v/68472/>
and the ensuing discussion in the RISC-V LLVM sync-up call. The
consensus agreed that the behaviour change in LLD introduced in D138550
that results in object files including arch attributes with unrecognised
extensions or versions of extensions is a regression and should be
treated as such. As it stands, this logic means that LLD will error out
if trying to link a RISC-V object file from LLVM HEAD (rv32i2p0/rv64i2p0)
with one from current GCC (rv32i2p1/rv64i2p1 by default).

There's a bigger discussion about exactly when to warn vs error and so
on, and how to control that, and this patch doesn't attempt to address
all those questions. It simply tries to fix the problem with a minimally
invasive change, intended to be cherry-picked for 16.0.x (ideally
16.0.0, but queued for 16.0.1 if we're too late in the release cycle).

As you can see from the test changes, although the changed logic is
mostly more permissive, it will reject some embedded arch strings that
were accepted before. Because the same logic was previously used for
parsing human-written -march as for the arch attribute (intended to be
stored in normalised form), various short-hand formats were previously
accepted. Maintaining support for such ill-formed attributes would
substantially complicate the logic, and given the previous
implementation was so much stricter in every other way, was surely a bug
rather than a design choice.

Surprisingly, the precise rules for how numbers can be embedded into
extension names isn't fully defined (there is a PR to the ISA manual
that is not yet merged
<https://github.com/riscv/riscv-isa-manual/pull/718>).
In the absence of specific criteria for rejecting extensions names that
would be ambiguous in abbreviated form,
`RISCVISAInfo::parseArchStringNormalized` just pulls out the version
information from the end of each extension description.

Differential Revision: https://reviews.llvm.org/D144353
2023-02-25 06:17:50 +00:00
Philipp Tomsich
f68f04d07c [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681
2023-02-24 21:40:42 +01:00
Manolis Tsamis
7b79e8d455 [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144647
2023-02-24 00:35:37 +01:00
Manolis Tsamis
f6262201d8 [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b

Depends on D144002

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144249
2023-02-24 00:17:58 +01:00
Manolis Tsamis
16a6cf6a99 [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144501
2023-02-22 11:15:40 +01:00
Manolis Tsamis
f5b484c56f [RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144496
2023-02-22 10:57:48 +01:00
Manolis Tsamis
bbb58a2302 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144002
2023-02-21 12:21:49 +01:00
Alex Bradbury
d41a73aa94 [RISCV][MC] Mark Zawrs extension as non-experimental
Support for the unratified 1.0-rc3 specification was introduced in
D133443. The specification has since been ratified (in November 2022
according to the recently ratified extensions list
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>.

A review of the diff
<https://github.com/riscv/riscv-zawrs/compare/V1.0-rc3...main> of the
1.0-rc3 spec vs the current/ratified document shows no changes to the
instruction encoding or naming. At one point, a note was added
<e84f42406a>
indicating Zawrs depends on the Zalrsc extension (not officially
specified, but I believe to be just the LR/SC instructions from the A
extension). The final text ended up as "The instructions in the Zawrs
extension are only useful in conjunction with the LR instructions, which
are provided by the A extension, and which we also expect to be provided
by a narrower Zalrsc extension in the future." I think it's consistent
with this phrasing to not require the A extension for Zawrs, which
matches what was implemented.

No intrinsics are implemented for Zawrs currently, meaning we don't need
to additionally review whether those intrinsics can be considered
finalised and ready for exposure to end users.

Differential Revision: https://reviews.llvm.org/D143507
2023-02-19 20:43:03 +00:00
Philip Reames
495b653480 [RISCV] Add missing plumbing and tests for zfa
Experimental support for the zfa extension was recently added in https://reviews.llvm.org/D141984. A couple of the normal test changes and clang plumbing got missed in that change. This commit updates the usual suspects.

Differential Revision: https://reviews.llvm.org/D144288
2023-02-17 17:56:30 -08:00
Philipp Tomsich
16a66af0a0 Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension"
This reverts commit d2918544a7fc4b5443879fe12f32a712e6dfe325.
2023-02-17 19:45:55 +01:00
Manolis Tsamis
d2918544a7 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Differential Revision: https://reviews.llvm.org/D144002
2023-02-17 19:45:22 +01:00
Philip Reames
22e199e6af [RISCV] Accept zicsr and zifencei command line options
This change adds the definition of the two extensions, but does not either a) make any instruction conditional on them or b) enabled the extensions by default. (The *instructions* do remain enabled by default per ISA version 2.0 which is our current default.)

This is meant to be a building block towards something like https://reviews.llvm.org/D141666, and in the meantime, address one of the most surprising of the current user experience warts. The current behavior of rejecting the extensions at the command line despite emitting code which appears to use them is surprising to anyone not deeply versed in the details of this situation.

Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions (these), but were no longer required by the base ISA. This change is described in “Preface to Document Version 20190608-Base-Ratified” from the specification document.

As LLVM currently implements only version 2.0 of the base specification, accepting these extensions at the command line introduces a configuration which doesn't actually match any spec version. It's a pretty harmless variant since the 2.0 extension definitions, to my knowledge, exactly match the text from the 2.0 I text before they were moved into standalone extensions in 2.1 of I. (The version numbering in that sentence is a tad confusing to say the least. Hopefully I got it right.)

It is worth noting that we already have numerous examples of accepting extensions in the march string which didn't exist in version of the spec document corresponding to our current base I version, so this doesn't set any new precedent.

Differential Revision: https://reviews.llvm.org/D143953
2023-02-16 10:41:41 -08:00
Manolis Tsamis
d4012bc43f [RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4041e11db3ec3611921d10150572a92689aa3154

Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143847
2023-02-14 20:25:47 +01:00
Philipp Tomsich
fc02eeb24f [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143439
2023-02-13 17:02:09 +01:00
Philipp Tomsich
04a2baf58f [RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143036
2023-02-13 16:28:26 +01:00
Philipp Tomsich
0bda199285 Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension"
This reverts commit 656188ddc4075eb50260607b3497589873f373d2.
2023-02-08 08:00:45 +01:00
Philipp Tomsich
b0c3132226 Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension"
This reverts commit 19a59099095b3cbc9846e5330de26fca0a44ccbe.
2023-02-08 08:00:34 +01:00
Philipp Tomsich
19a5909909 [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Differential Revision: https://reviews.llvm.org/D143439
2023-02-08 07:57:27 +01:00
Philipp Tomsich
656188ddc4 [RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143394

Differential Revision: https://reviews.llvm.org/D143036
2023-02-08 07:57:27 +01:00
Philipp Tomsich
e25b30d90a [RISCV] Add vendor-defined XTHeadBa (address-generation) extension
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba.  It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBa is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143029
2023-02-08 07:54:52 +01:00
Philipp Tomsich
9ac73d1251 [RISCV] Fix wrong comment style. NFC 2023-01-29 22:00:32 +01:00
Philipp Tomsich
4732e3cc1d [RISCV] Alphabetize X-extensions (and add a comment). NFC. 2023-01-29 21:55:12 +01:00
Craig Topper
3d7a59bdc0 [RISCV] Bump Zca, Zcb, Zcd, Zcf version to 1.0.
Differential Revision: https://reviews.llvm.org/D142596
2023-01-28 22:04:34 -08:00
WuXinlong
42c36da9c9 [RISCV] Add MC support of RISCV Zcb Extension
This patch add the instructions of Zcb extension.

Instructions in zcb extensions shorten part of bit manipulation instructions.

Co-authored-by: Craig Topper <craig.topper@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D131141
2023-01-26 12:54:00 -08:00
Elena Lepilkina
31ee6ae059 [llvm-objdump] Fix reporting error for processing target features
Differential Revision: https://reviews.llvm.org/D142003
2023-01-18 16:56:51 +03:00
Elena Lepilkina
537cdf92c4 [llvm-objdump][RISCV] Use new common method to parse ARCH RISCV attribute
Differential Revision: https://reviews.llvm.org/D139553
2023-01-16 16:57:55 +03:00
Kito Cheng
f601039e81 [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march
RISC-V supports `-march`, `-mtune`, and `-mcpu`: `-march` provides the
architecture extension information, `-mtune` provide the pipeline model, and
`-mcpu` provides both.

What's the priority among those options for now(w/o this patch)?

Pipeline model:
- Take from `-mtune` if present.
- Take from `-mcpu` if present
- Use the default pipeline model: `generic-rv32` or `generic-rv64`
Architecture extension has quite complicated behavior now:
- Take union from `-march` and `-mcpu` if both are present.
- Take from `-march` if present.
- Take from `-mcpu` if present.
- Implied from `-mabi` if present.
- Use the default architecture depending on the target triple

We treat `-mcpu`/`-mtune` and `-mcpu`/`-march` differently, and it's
kind of counterintuitive: -march is explicitly specified but ignored.

This patch adjusts the priority between `-mcpu`/`-march`, letting it use
architecture extension information from `-march` if it's present.

So the priority of architecture extension information becomes:
- Take from `-march` if present.
- Take from `-mcpu` if present.
- Implied from `-mabi` if present.
- Use the default architecture depending on the target triple

And this also match what we implement in RISC-V GCC too.

Reviewed By: craig.topper, MaskRay

Differential Revision: https://reviews.llvm.org/D140693
2023-01-13 23:58:31 +08:00
Kito Cheng
f4c887c3a8 [RISCV] Add H extension
`h` was the prefix of multi-letter extension name, but it become a
extension name in later RISC-V isa spec.

Fortunately we don't have any extension really defined is prefixed
with `h`, so we can just change that.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136817
2023-01-10 09:52:03 +08:00
serge-sans-paille
38818b60c5
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
Use deduction guides instead of helper functions.

The only non-automatic changes have been:

1. ArrayRef(some_uint8_pointer, 0) needs to be changed into ArrayRef(some_uint8_pointer, (size_t)0) to avoid an ambiguous call with ArrayRef((uint8_t*), (uint8_t*))
2. CVSymbol sym(makeArrayRef(symStorage)); needed to be rewritten as CVSymbol sym{ArrayRef(symStorage)}; otherwise the compiler is confused and thinks we have a (bad) function prototype. There was a few similar situation across the codebase.
3. ADL doesn't seem to work the same for deduction-guides and functions, so at some point the llvm namespace must be explicitly stated.
4. The "reference mode" of makeArrayRef(ArrayRef<T> &) that acts as no-op is not supported (a constructor cannot achieve that).

Per reviewers' comment, some useless makeArrayRef have been removed in the process.

This is a follow-up to https://reviews.llvm.org/D140896 that introduced
the deduction guides.

Differential Revision: https://reviews.llvm.org/D140955
2023-01-05 14:11:08 +01:00
wangpc
c570287fbf [RISCV][NFC] Move RISCVISAInfo back to Support
So that there is no cyclic dependency if we want to use it in
tablegen.

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D140529
2023-01-03 13:55:39 +08:00
Archibald Elliott
f09cf34d00 [Support] Move TargetParsers to new component
This is a fairly large changeset, but it can be broken into a few
pieces:
- `llvm/Support/*TargetParser*` are all moved from the LLVM Support
  component into a new LLVM Component called "TargetParser". This
  potentially enables using tablegen to maintain this information, as
  is shown in https://reviews.llvm.org/D137517. This cannot currently
  be done, as llvm-tblgen relies on LLVM's Support component.
- This also moves two files from Support which use and depend on
  information in the TargetParser:
  - `llvm/Support/Host.{h,cpp}` which contains functions for inspecting
    the current Host machine for info about it, primarily to support
    getting the host triple, but also for `-mcpu=native` support in e.g.
    Clang. This is fairly tightly intertwined with the information in
    `X86TargetParser.h`, so keeping them in the same component makes
    sense.
  - `llvm/ADT/Triple.h` and `llvm/Support/Triple.cpp`, which contains
    the target triple parser and representation. This is very intertwined
    with the Arm target parser, because the arm architecture version
    appears in canonical triples on arm platforms.
- I moved the relevant unittests to their own directory.

And so, we end up with a single component that has all the information
about the following, which to me seems like a unified component:
- Triples that LLVM Knows about
- Architecture names and CPUs that LLVM knows about
- CPU detection logic for LLVM

Given this, I have also moved `RISCVISAInfo.h` into this component, as
it seems to me to be part of that same set of functionality.

If you get link errors in your components after this patch, you likely
need to add TargetParser into LLVM_LINK_COMPONENTS in CMake.

Differential Revision: https://reviews.llvm.org/D137838
2022-12-20 11:05:50 +00:00
Kazu Hirata
405fc404bf [ADT] Don't including None.h (NFC)
These source files no longer use None, so they do not need to include
None.h.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-06 20:14:51 -08:00
Kazu Hirata
aadaaface2 [llvm] Use std::nullopt instead of None (NFC)
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated.  The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:44 -08:00
Kazu Hirata
7c421b53d1 [Support] Use std::optional in RISCVISAInfo.cpp (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-11-25 21:48:18 -08:00
Fangrui Song
bc0caabef5 RISCVISAInfo: Internalize struct FindByName 2022-11-23 17:22:49 -08:00
WuXinlong
0dbc52a0ab Add MC support of RISCV Zcd Extension
This patch add the instructions of Zcd extension.

Zcd is a subset of C Ext which include the double-precision floating-point instructions (c.fld, c.fldsp, c.fsd, c.fsdsp).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134177
2022-11-24 05:48:06 +08:00
WuXinlong
16bf359a3f Add MC support of RISCV Zcf Extension
This patch add the instructions of Zcf extension.

Zcf is a subset of C Ext which include the single-precision floating-point instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134176
2022-11-23 15:09:02 +08:00