24929 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
fb03a92c33 Be less aggressive about hinting in RAFast.
In particular, don't spill dirty registers only to satisfy a hint. It is
not worth it.

The attached test case provides an example where the fast allocator
would spill a register when other registers are available.

llvm-svn: 132900
2011-06-13 03:26:46 +00:00
Jakob Stoklund Olesen
f4f66f36c7 Include callee-saved registers in debug output.
llvm-svn: 132899
2011-06-13 03:26:42 +00:00
Rafael Espindola
51d2d7aabc Fix invalid uses of Twine. Hopefully this fixes the problem that Takumi is
having.

llvm-svn: 132898
2011-06-13 03:09:13 +00:00
Nadav Rotem
504cf0cde2 Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd
types such as i33 were rounded to i32. Originated from Duncan's testcase.

llvm-svn: 132893
2011-06-12 14:56:55 +00:00
Nadav Rotem
083837e729 Improve the generated code by getCopyFromPartsVector for promoted integer types.
Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors:  i8 -> <1 x i1> (from Duncan's
testcase).

llvm-svn: 132892
2011-06-12 14:49:38 +00:00
Rafael Espindola
2f3c2fe7c5 Really fix the fall-through logic.
Add a triple to the tests.

llvm-svn: 132885
2011-06-12 05:57:01 +00:00
Rafael Espindola
653a07206d Fix silly bug I introduce in the previous commit. Fixes debug builds.
llvm-svn: 132883
2011-06-12 05:26:32 +00:00
Rafael Espindola
defd4b0875 AnalyzeBranch doesn't change which successors a bb has, just the order
we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882
2011-06-12 03:20:32 +00:00
Chad Rosier
79044dbebf Revert r132871.
llvm-svn: 132872
2011-06-11 02:27:46 +00:00
Chad Rosier
5793b53027 Typo.
llvm-svn: 132871
2011-06-11 02:16:36 +00:00
Eric Christopher
eb964516c3 80-col cleanups.
llvm-svn: 132863
2011-06-10 23:05:08 +00:00
Rafael Espindola
0f62e4c428 Removed tabs. Also fixed my editor...
llvm-svn: 132857
2011-06-10 21:01:53 +00:00
Cameron Zwarich
8b58a83889 Rename the ParmContext enum values to make a bit more sense and add a small
comment on their meaning.

llvm-svn: 132854
2011-06-10 20:37:36 +00:00
Cameron Zwarich
6221139453 Remove tabs.
llvm-svn: 132853
2011-06-10 20:31:39 +00:00
Cameron Zwarich
86ceec1b42 Remove a pointless const_cast.
llvm-svn: 132852
2011-06-10 20:30:08 +00:00
Rafael Espindola
1ffadd7809 Remove duplicated test.
Thanks Bob Wilson for noticing it!

llvm-svn: 132851
2011-06-10 20:08:23 +00:00
Chad Rosier
b90a43d266 Ensure that EmitGlobalVariable is correctly differentiating between declarations
and definitions when emitting global variables.  This was causing global 
declarations to be emitted as if they were definitions.
Fixes <rdar://problem/9429892>.

llvm-svn: 132825
2011-06-10 00:53:15 +00:00
Rafael Espindola
9e97a895f3 Make the optional verification step more strict.
llvm-svn: 132822
2011-06-09 23:55:56 +00:00
Rafael Espindola
c9e93a44be Avoid a gcc warning about multiline comments.
llvm-svn: 132821
2011-06-09 23:51:45 +00:00
Rafael Espindola
c735f13368 On last fix to the early tail duplication.
With this I am able to bootstrap clang with early tail duplication enabled
for any small bb and setting tail-dup-size to a relatively large value(8) to
stress this code.

llvm-svn: 132816
2011-06-09 23:22:56 +00:00
Rafael Espindola
81512fc1bb Also consider phi nodes when deciding if a register is live out.
llvm-svn: 132814
2011-06-09 22:53:47 +00:00
Eli Friedman
1877ac9937 Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809.
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.

llvm-svn: 132809
2011-06-09 22:14:44 +00:00
Rafael Espindola
c90a32a4e6 AnalyzeBranch modifies the bb, but we don't want to modify a bb with
eh edges. Swap the order of the checks to avoid it.

llvm-svn: 132806
2011-06-09 21:43:25 +00:00
Rafael Espindola
887fc1bdeb A PHI in this basic block is a use in another basic block.
llvm-svn: 132805
2011-06-09 20:55:41 +00:00
Rafael Espindola
73f93930e0 Refactor some checks into shouldTailDuplicate. Update comments.
No functionality change.

llvm-svn: 132798
2011-06-09 19:54:42 +00:00
Eric Christopher
cafa08cbf3 Recommit r132764 since it didn't cause the windows buildbot failures.
llvm-svn: 132776
2011-06-09 15:39:01 +00:00
Eric Christopher
76fd742d16 Temporarily revert 132764 to see if it fixes the Windows buildbot.
llvm-svn: 132771
2011-06-09 06:29:54 +00:00
Eric Christopher
11edab6a46 If the alignment of the byval argument is greater than the alignment
of the frame then increase the maximum alignment of the frame to
match.

Fixes PR6965

llvm-svn: 132764
2011-06-09 00:15:19 +00:00
Eric Christopher
0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction.
No functional change.

Part of PR6965

llvm-svn: 132763
2011-06-08 23:55:35 +00:00
Andrew Trick
6ed0c63559 Remove a temporary test case probe in CheckForLiveRegDef.
llvm-svn: 132751
2011-06-08 15:19:49 +00:00
Rafael Espindola
eabd18b931 Fix count.
llvm-svn: 132749
2011-06-08 14:23:19 +00:00
Rafael Espindola
dfbf6de747 Count how many phis we are creating.
llvm-svn: 132748
2011-06-08 14:13:31 +00:00
Cameron Zwarich
2e252de512 Fix an issue where the two-address conversion pass incorrectly rewrites untied
operands to an early clobber register. This fixes <rdar://problem/9566076>.

llvm-svn: 132738
2011-06-07 23:54:00 +00:00
Rafael Espindola
c85e0d81e4 Fix a silly error I introduce in r131951.
Fixes PR10095.

llvm-svn: 132735
2011-06-07 23:26:45 +00:00
Andrew Trick
0af2e47310 Fix a merge bug in preRAsched for handling physreg aliases.
I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.

llvm-svn: 132701
2011-06-07 00:38:12 +00:00
Jakob Stoklund Olesen
df476270eb Simplify local live range splitting's safeguard to fix PR10070.
When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.

This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.

llvm-svn: 132697
2011-06-06 23:55:20 +00:00
Jakob Stoklund Olesen
0cde8eb9e2 Get allocation orders from RegisterClassInfo when possible.
Only target-dependent hints require callbacks. The RCI allocation order
has CSR aliases last according to their order of appearance in the
getCalleeSavedRegs list. This can depend on the calling convention.

This way, AllocationOrder::next doesn't have to check for reserved
registers, and CSRs are always allocated last, even with weird calling
conventions.

llvm-svn: 132690
2011-06-06 21:02:04 +00:00
Nadav Rotem
c807fa5687 Add methods to support the integer-promotion of vector types. Methods to
legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.

llvm-svn: 132689
2011-06-06 20:55:56 +00:00
Stuart Hastings
bee6fcc5aa Avoid FGETSIGN of 80-bit types. Fixes PR10085.
llvm-svn: 132681
2011-06-06 16:44:31 +00:00
Jakob Stoklund Olesen
b7657d0225 Don't try to be clever, just preserve the target's allocation order.
The order of registers returned by getCalleeSavedRegs is used to lay out
the fixed stack slots for CSRs. Some targets like their CSRs used from
one end, and some targets want them used from the other end.

When computing an allocation order, simply preserve the relative
ordering of CSRs that the target specifies in its allocation order.
Reordering CSRs would break some targets, ARM in particular.

We still place volatiles before the CSRs, providing slightly better
results with different calling conventions.

llvm-svn: 132680
2011-06-06 16:36:30 +00:00
Eli Friedman
bd375f1a3f PR10077: fix fast-isel of extractvalue of aggregate constants.
llvm-svn: 132676
2011-06-06 05:46:34 +00:00
Benjamin Kramer
440c3b7306 Use path API for path concatenation.
llvm-svn: 132668
2011-06-05 14:36:47 +00:00
Nadav Rotem
06bd6d304e TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts).
llvm-svn: 132649
2011-06-04 20:58:08 +00:00
Nadav Rotem
78d19bebe6 TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.
(only happens when using the -promote-elements option).

The correct legalization order is to first try to promote element. Next, we try
to widen vectors.

llvm-svn: 132648
2011-06-04 20:32:01 +00:00
Jakob Stoklund Olesen
b8bf3c0f8b Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

llvm-svn: 132581
2011-06-03 20:34:53 +00:00
Jakob Stoklund Olesen
3460ae88b2 Preserve the original ordering when a CSR has multiple aliases.
Previously, these aliases would be ordered alphabetically. (BH, BL)

Print out the computed allocation orders.

llvm-svn: 132580
2011-06-03 20:34:50 +00:00
Eric Christopher
fbff0e4f26 Add a TODO about memory operands.
llvm-svn: 132559
2011-06-03 17:21:23 +00:00
Jakob Stoklund Olesen
4b0bb8396a Avoid calling TRI->getAllocatableSet in RAFast.
When compiling a program with lots of small functions like
483.xalancbmk, this makes RAFast 11% faster.

Add some comments to clarify the difference between unallocatable and
reserved registers. It's quite subtle.

The fast register allocator depends on EFLAGS' not being allocatable on
x86. That way it can completely avoid tracking liveness, and it won't
mind when there are multiple uses of a single def.

llvm-svn: 132514
2011-06-02 23:41:40 +00:00
Eric Christopher
de9399bf76 Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939

llvm-svn: 132510
2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
75703ca76f Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508
2011-06-02 23:07:20 +00:00