169120 Commits

Author SHA1 Message Date
Josh Stone
f446facab0 [GlobalISel] Lower dbg.declare into indirect DBG_VALUE
Summary:
D31439 changed the semantics of dbg.declare to take the address of a
variable as the first argument, making it indirect.  It specifically
updated FastISel for this change here:

https://reviews.llvm.org/D31439#change-WVArzi177jPl

GlobalISel needs to follow suit, or else it will be missing a level of
indirection in the generated debuginfo.  This problem was seen in a Rust
debuginfo test on aarch64, since GlobalISel is used at -O0 for aarch64.

https://github.com/rust-lang/rust/issues/49807
https://bugzilla.redhat.com/show_bug.cgi?id=1611597
https://bugzilla.redhat.com/show_bug.cgi?id=1625768

Reviewers: dblaikie, aprantl, t.p.northover, javed.absar, rnk

Reviewed By: rnk

Subscribers: #debug-info, rovka, kristof.beyls, JDevlieghere, llvm-commits, tstellar

Differential Revision: https://reviews.llvm.org/D51749

llvm-svn: 341969
2018-09-11 17:52:01 +00:00
Johannes Doerfert
8b7b743cc1 [LoopInfo][FIX] Remove leftover dump in unit test
llvm-svn: 341968
2018-09-11 17:49:43 +00:00
Josh Stone
aca532f14d Test commit: remove trailing whitespace
llvm-svn: 341966
2018-09-11 17:28:43 +00:00
Matt Morehouse
40fbdd0c4f Revert "[SanitizerCoverage] Create comdat for global arrays."
This reverts r341951 due to bot breakage.

llvm-svn: 341965
2018-09-11 17:20:14 +00:00
Craig Topper
12fd6bd4ad [InstCombine] Use dyn_cast instead of match(m_Constant). NFC
llvm-svn: 341962
2018-09-11 16:51:26 +00:00
Craig Topper
a57bb61a3e [InstCombine] Support (mul (sext x), cst) --> (sext (mul x, cst')) and (mul (zext x), cst) --> (zext (mul x, cst')) for vectors constants.
Similar to D51236, but for mul instead of add.

Differential Revision: https://reviews.llvm.org/D51900

llvm-svn: 341961
2018-09-11 16:51:24 +00:00
Jessica Paquette
49d190f6f8 [NFC] Fix typo in comment
Fore -> For

llvm-svn: 341960
2018-09-11 16:38:46 +00:00
Jessica Paquette
050d1ac4a6 [MachineOutliner][NFC] Factor out instruction mapping into its own function
Just some tidy-up. Pull the mapper stuff into `populateMapper`. This makes it
a bit easier to read what's going on in `runOnModule`.

llvm-svn: 341959
2018-09-11 16:33:46 +00:00
Craig Topper
d7362a3e5f [X86] Correct the one use check from r341915.
The one use check should be on the bitcast, not the input to the bitcast.

llvm-svn: 341956
2018-09-11 16:05:03 +00:00
Alexandros Lamprineas
db18e972d7 [GVNHoist] Re-enable GVNHoist by default
Rebase rL340922 since https://bugs.llvm.org/show_bug.cgi?id=38807
has been fixed by rL341947.

llvm-svn: 341954
2018-09-11 15:55:45 +00:00
Roman Lebedev
baf2628043 [DagCombine][NFC] Some more tests fo for X % C == 0 (UREM case) transform
For https://reviews.llvm.org/D50222

Patch by: hermord (Dmytro Shynkevych)!

llvm-svn: 341953
2018-09-11 15:34:26 +00:00
Simon Atanasyan
16c2311c59 [MIPS] Fix illegal type assert in single-float mode
An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in
single-float mode. This would trigger an "Unexpected illegal type!"
assert.

Patch by Dan Ravensloft.

Differential revision: https://reviews.llvm.org/D51810

llvm-svn: 341952
2018-09-11 15:32:47 +00:00
Matt Morehouse
eac270caf4 [SanitizerCoverage] Create comdat for global arrays.
Summary:
Place global arrays in comdat sections with their associated functions.
This makes sure they are stripped along with the functions they
reference, even on the BFD linker.

Reviewers: eugenis

Reviewed By: eugenis

Subscribers: eraman, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D51902

llvm-svn: 341951
2018-09-11 15:23:14 +00:00
Alexandros Lamprineas
96762b37e1 [MemorySSAUpdater] Avoid creating self-referencing MemoryDefs
Fix for https://bugs.llvm.org/show_bug.cgi?id=38807, which occurred
while compiling SemaTemplateInstantiate.cpp with clang and GVNHoist
enabled. In the following example:

      1=def(entry)
      /        \
2=def(1)       4=def(1)
3=def(2)       5=def(4)

When removing the MemoryDef 2=def(1) from its basic block, and just
before adding it to the end of the parent basic block, we first
replace all its uses with the defining memory access:

3=def(2) -> 3=def(1)

Then we call insertDef for adding 2=def(1) to the parent basic block,
where we replace the uses of 1=def(entry) with 2=def(1). Doing so we
create a self reference:

2=def(1) -> 2=def(2)  (bad)
3=def(1) -> 3=def(2)  (ok)
4=def(1) -> 4=def(2)  (ok)

Differential Revision: https://reviews.llvm.org/D51801

llvm-svn: 341947
2018-09-11 14:29:59 +00:00
Nico Weber
e2745b5d86 pdb output: Initialize padding in PublicsStreamHeader.
Makes the produced pdbs more deterministic; before they'd contain 2 arbitary
bytes where this padding was.

Also reorder initialization to match the order of the fields in the struct (nfc)

llvm-svn: 341945
2018-09-11 14:11:52 +00:00
Nico Weber
f48e961d23 Make malformed-machos.test pass on my Mac.
For some reason, llvm-objdump defaults to -arch=i386 on this system while
the test checks x86_64 output. Explicitly pass -arch=x86_64.

llvm-svn: 341944
2018-09-11 14:10:33 +00:00
Roman Lebedev
de9d787131 [Hexagon] [Test] Remove undef and infinite loop from test
Summary:
The undef and the infinite loop at the end cause this test to be translated
unpredictably. In particular, the checked-for `mpy` disappears under
certain legal optimizations (e.g. the one in D50222).
Since the use of these constructs is not relevant to the behavior tested,
according to the header comment, this change, suggested by @kparzysz,
eliminates them.

Was initially committed in r341046, but was reverted.

Patch by: hermord (Dmytro Shynkevych)!

Reviewers: kparzysz

Reviewed By: kparzysz

Subscribers: lebedev.ri, llvm-commits, kparzysz

Differential Revision: https://reviews.llvm.org/D50944

llvm-svn: 341943
2018-09-11 14:06:14 +00:00
Sam Parker
01db2983cd [ARM] Add smlald support in ARMParallelDSP
Search from i64 reducing phis, as well as i32, to allow the
generation of smlald instructions.

Differential Revision: https://reviews.llvm.org/D51101

llvm-svn: 341941
2018-09-11 14:01:22 +00:00
Sanjay Patel
e368f46788 [AArch64] test codegen for unsigned saturated add; NFC
This is identical to the tests added for x86 at rL341845.
A semi-generic DAGCombine should improve things universally.

llvm-svn: 341935
2018-09-11 13:21:28 +00:00
Petar Jovanovic
5abf4bb552 [MIPS] ORC JIT support
This patch adds support for ORC JIT for mips/mips64 architecture.
In common code $static is changed to __ORCstatic because on MIPS
architecture "$" is a reserved character.

Patch by Luka Ercegovcevic

Differential Revision: https://reviews.llvm.org/D49665

llvm-svn: 341934
2018-09-11 13:10:04 +00:00
Sam Parker
945604d511 [ARM] Enable ARMCodeGenPrepare by default
We've had the pass enabled downstream for a couple of weeks and it
seems to be okay, so enable it by default.

Differential Revision: https://reviews.llvm.org/D51920

llvm-svn: 341932
2018-09-11 12:45:43 +00:00
Alexander Timofeev
db7ee7660a [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
Differential revision: https://reviews.llvm.org/D51734
Reviewers: rampitec

llvm-svn: 341928
2018-09-11 11:56:50 +00:00
Johannes Doerfert
ae3cfeb3ad [FuncAttrs] Remove "access range attributes" for read-none functions
The presence of readnone and an access range attribute (argmemonly,
inaccessiblememonly, inaccessiblemem_or_argmemonly) is considered an
error by the verifier. This seems strict but also not wrong. This
patch makes sure function attribute detection will remove all access
range attributes for readnone functions.

llvm-svn: 341927
2018-09-11 11:51:29 +00:00
Johannes Doerfert
a58e9214ac [LoopInfo] Fix Loop::getLoopID() for loops with multiple latches
The previous implementation traversed all loop blocks and bailed if one
was not a latch block. Since we are only interested in latch blocks, we
should only traverse those.

llvm-svn: 341926
2018-09-11 11:44:17 +00:00
Simon Atanasyan
32d8d1bf04 [mips] Add a pattern for 64-bit GPR variant of the rdhwr instruction
MIPS ISAs start to support third operand for the `rdhwr` instruction
starting from Revision 6. But LLVM generates assembler code with
three-operands version of this instruction on any MIPS64 ISA. The third
operand is always zero, so in case of direct code generation we get
correct code.

This patch fixes the bug by adding an instruction alias. The same alias
already exists for 32-bit ISA.

Ideally, we also need to reject three-operands version of the `rdhwr`
instruction in an assembler code if ISA revision is less than 6. That is
a task for a separate patch.

This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861)

Differential revision: https://reviews.llvm.org/D51773

llvm-svn: 341919
2018-09-11 09:57:25 +00:00
Max Kazantsev
bf00f03f56 [NFC] Sanitizing asserts for OrderedBasicBlock
llvm-svn: 341917
2018-09-11 08:46:19 +00:00
Craig Topper
844f035e1e [X86] In combineMOVMSK, look through int->fp bitcasts before callling SimplifyDemandedBits.
MOVMSKPS and MOVMSKPD both take FP types, but likely the operations before it are on integer types with just a int->fp bitcast between them. If the bitcast isn't used by anything else and doesn't change the element width we can look through it to simplify the integer ops.

llvm-svn: 341915
2018-09-11 08:20:02 +00:00
Dean Michael Berris
174d2cf771 [XRay] Ensure lambda outlives llvm::function_ref
Follow-up to D51912.

llvm-svn: 341912
2018-09-11 08:03:30 +00:00
Dean Michael Berris
ec605d3846 [XRay] Write the TSC along with CPUID
Fixes builds in non-little-endian systems.

This is a follow-up to D51911.

llvm-svn: 341909
2018-09-11 07:27:59 +00:00
Craig Topper
85210311ba [X86] Add test cases inspired by PR38840.
These are test cases inspired by sequences like below for extracting the same bit from every vector element and checking for all zeros/ones.

define i1 @and256_x8(<8 x i32>) {
    %a = trunc <8 x i32> %0 to <8 x i1>
    %b = bitcast <8 x i1> %a to i8
    %d = icmp eq i8 %b, -1
    ret i1 %d
}

This is what the above looks like after InstCombine.

define i1 @and256_x8_opt(<8 x i32>) {
  %2 = and <8 x i32> %0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
  %a = icmp ne <8 x i32> %2, zeroinitializer
  %b = bitcast <8 x i1> %a to i8
  %d = icmp eq i8 %b, -1
  ret i1 %d
}

llvm-svn: 341908
2018-09-11 07:23:29 +00:00
Dean Michael Berris
985c2b9226 [XRay] Use FDR Records+Visitors for Trace Loading
Summary:
In this change, we overhaul the implementation for loading
`llvm::xray::Trace` objects from files by using the combination of
specific FDR Record types and visitors breaking up the logic to
reconstitute an execution trace from flight-data recorder mode traces.

This change allows us to handle out-of-temporal order blocks as written
in files, and more consistently recreate an execution trace spanning
multiple blocks and threads. To do this, we use the `WallclockRecord`
associated with each block to maintain temporal order of blocks, before
attempting to recreate an execution trace.

The new addition in this change is the `TraceExpander` type which can be
thought of as a decompression/decoding routine. This allows us to
maintain the state of an execution environment (thread+process) and
create `XRayRecord` instances that fit nicely into the `Trace`
container. We don't have a specific unit test for the TraceExpander
type, since the end-to-end tests for the `llvm-xray convert` tools
already cover precisely this codepath.

This change completes the refactoring started with D50441.

Depends on D51911.

Reviewers: mboerger, eizan

Subscribers: mgorny, hiraditya, mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D51912

llvm-svn: 341906
2018-09-11 06:45:59 +00:00
Dean Michael Berris
d2c50408d4 [XRay] Add TSC to NewCPUId Records
Summary:
This more correctly reflects the data written by the FDR mode runtime.

This is a continuation of the work in D50441.

Reviewers: mboerger, eizan

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D51911

llvm-svn: 341905
2018-09-11 06:36:51 +00:00
Max Kazantsev
9aacaffd98 [NFC] Specify test's option to reduce reliance on defaults
llvm-svn: 341904
2018-09-11 06:34:43 +00:00
Max Kazantsev
90edc98c58 [NFC] Rename variable
llvm-svn: 341901
2018-09-11 05:10:01 +00:00
JF Bastien
c0d77e80ac NCF: use bit_cast in IntervalMap
This use is sketchy because it basically reinterprets a pointer to another pointer, but right now it's hiding in a union. After this change it'll be easy to grep for bit_cast of a pointer and un-sketch things if we want. This patch therefore obeys the law of conservation of sketch, with minor improvement.

llvm-svn: 341900
2018-09-11 04:52:21 +00:00
Heejin Ahn
a9076e35d4 [XRay] Add missing LLVMTestingSupport target_link_libraries
Without this builds with `-DLLVM_LINK_LLVM_DYLIB=ON` fail.

llvm-svn: 341899
2018-09-11 04:48:08 +00:00
Matt Arsenault
d0cf1b26d4 AMDGPU: Fix r600 test
llvm-svn: 341898
2018-09-11 04:39:16 +00:00
JF Bastien
49ddd5aca1 NFC: use bit_cast more in AArch64AddressingModes
The was previously committed as r341749 then reverted as r341750 because
bit_cast needed to do its own thing to check is_trivially_copyable on GCC 4.x.
This is now done and std;:array should now get accepted.

llvm-svn: 341897
2018-09-11 04:08:05 +00:00
Serguei Katkov
5f4a9e9ea0 [LICM] Avoid duplicate work during building AliasSetTracker
Currently we re-use cached info from sub loops or traverse them
to populate AliasSetTracker. But after that we traverse all basic blocks
from the current loop. This is redundant work.

All what we need is traversing the all basic blocks from the loop except
those which are used to get the data from the cache.

This should improve compile time only.

Reviewers: mkazantsev, reames, kariddi, anna
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51715

llvm-svn: 341896
2018-09-11 04:07:36 +00:00
Matt Arsenault
796b0e7a90 AMDGPU: Remove leftovers from configurable address spaces
llvm-svn: 341895
2018-09-11 04:00:49 +00:00
Matt Arsenault
99c780159d AMDGPU: Don't error on out of bounds address spaces
We should never abort on valid IR. The most reasonable
interpretation of an arbitrary address space pointer is
probably some kind of special subset of global memory.

llvm-svn: 341894
2018-09-11 04:00:41 +00:00
Max Kazantsev
e6413919ce [IndVars][NFC] Refactor to make modifications of Changed transparent
IndVarSimplify's design is somewhat odd in the way how it reports that
some transform has made a change. It has a `Changed` field which can
be set from within any function, which makes it hard to track whether or
not it was set properly after a transform was made. It leads to oversights
in setting this flag where needed, see example in PR38855.

This patch removes the `Changed` field, turns it into a local and unifies
the signatures of all relevant transform functions to return boolean value
which designates whether or not this transform has made a change.

Differential Revision: https://reviews.llvm.org/D51850
Reviewed By: skatkov

llvm-svn: 341893
2018-09-11 03:57:22 +00:00
Philip Reames
1f52e38e8e [LICM] (re-)simplify code using MemoryLocation API [NFC]
I'd made exactly this same change before, but it appears to have been accidentally reverted in another change.  (I'm assuming accidental since it was without comment or test case, and in an unrelated change.)

llvm-svn: 341892
2018-09-11 03:28:28 +00:00
David Blaikie
4ec5a9159b llvm-symbolizer: Fix bug related to TUs interfering with symbolizing
With the merge of TUs and CUs into a single container, some code that
relied on the CU range having an ordered range of contiguous addresses
(for locating a CU at a given offset) broke. But the units from
debug_info (currently only CUs, but CUs and TUs in DWARFv5) are in a
contiguous sub-range of that container - searching only through that
subrange is still valid & so do that.

llvm-svn: 341889
2018-09-11 02:04:45 +00:00
Peter Collingbourne
c7d281905b Prevent Constant Folding From Optimizing inrange GEP
This patch does the following things:

1. update SymbolicallyEvaluateGEP so that it bails out if it cannot preserve inrange arribute;
2. update llvm/test/Analysis/ConstantFolding/gep.ll to remove UB in it;
3. remove inaccurate comment above ConstantFoldInstOperandsImpl in llvm/lib/Analysis/ConstantFolding.cpp;
4. add a new regression test that makes sure that no optimizations change an inrange GEP in an unexpected way.

Patch by Zhaomo Yang!

Differential Revision: https://reviews.llvm.org/D51698

llvm-svn: 341888
2018-09-11 01:53:36 +00:00
Dean Michael Berris
dd01efc56d [XRay] Add the llvm-xray fdr-dump implementation
Summary:
In this change, we implement a `BlockPrinter` which orders records in a
Block that's been indexed by the `BlockIndexer`. This is used in the
`llvm-xray fdr-dump` tool which ties together the various types and
utilities we've been working on, to allow for inspection of XRay FDR
mode traces both with and without verification.

This change is the final step of the refactoring of D50441.

Reviewers: mboerger, eizan

Subscribers: mgorny, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D51846

llvm-svn: 341887
2018-09-11 00:22:53 +00:00
Jessica Paquette
a80d6faa10 Add REQUIRES line to machine-size-remarks
Just was made aware that this is necessary for tests outside of
the X86 subdirectory. Add a REQUIRES line to make sure bots that
don't enable x86 are happy.

llvm-svn: 341885
2018-09-10 23:53:08 +00:00
Craig Topper
3de8d592d1 [InstCombine] Add testcases for (mul (sext x), cst) --> (sext (mul x, cst')) and (mul (zext x), cst) --> (zext (mul x, cst')) for vectors constants.
If the multiply won't overflow in the original type we can use a smaller mul and sign extend afterwards. We don't currently support this for vector constants.

llvm-svn: 341884
2018-09-10 23:48:21 +00:00
Alina Sbirlea
116caa2920 [InstCombine] Partially revert rL341674 due to PR38897.
Summary:
Revert min/max changes in rL341674 dues to high compile times causing timeouts (PR38897).
Checking in to unblock failing builds. Patch available for post-commit review and re-revert once resolved.
Working on a smaller reproducer for PR38897.

Reviewers: craig.topper, spatel

Subscribers: sanjoy, jlebar, llvm-commits

Differential Revision: https://reviews.llvm.org/D51897

llvm-svn: 341883
2018-09-10 23:47:21 +00:00
Jessica Paquette
cd7bd8262a Explicitly state triple in machine-size-remarks.ll
A bot was unhappy with the x86 triple there before. Set it explicitly to
x86_64-apple-darwin just to get something consistent.

Example failure:
http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/16846

llvm-svn: 341882
2018-09-10 23:30:53 +00:00