1 Commits

Author SHA1 Message Date
Carl Ritson
5cc4b05380
[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)
Improve waitcnt merging in ML kernel loops by increasing latencies on
VALU writes to SGPRs.
Specifically this helps with the case of V_CMP output feeding V_CNDMASK
instructions.
2026-02-03 11:10:28 +09:00