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121 Commits

Author SHA1 Message Date
Matt Arsenault
b0a227049f AMDGPU/GlobalISel: Fix shift legalization for non-power-of-2 
clampScalar doesn't do anything for non-power-of-2 in range.
There should probably be a combination rule to reduce the number
of matching rules.

llvm-svn: 353526
 2019-02-08 15:06:24 +00:00
Matt Arsenault
0f2debb1c2 AMDGPU/GlobalISel: Fix non-power-of-2 implicit_def 
llvm-svn: 353522
 2019-02-08 14:46:27 +00:00
Matt Arsenault
dc88a2ce35 AMDGPU/GlobalISel: Don't use a copy in addrspacecast lowering 
llvm-svn: 353516
 2019-02-08 14:16:11 +00:00
Matt Arsenault
a8b4339c2f AMDGPU/GlobalISel: Legalize addrspacecast 
Use a placeholder constant for now on targets
that need the load from the queue ptr.

llvm-svn: 353497
 2019-02-08 02:40:47 +00:00
Matt Arsenault
fbec8fe93b GlobalISel: Implement narrowScalar for shift main type 
This is pretty much directly ported from SelectionDAG. Doesn't include
the shift by non-constant but known bits version, since there isn't a
globalisel version of computeKnownBits yet.

This shows a disadvantage of targets not specifically which type
should be used for the shift amount. If type 0 is legalized before
type 1, the operations on the shift amount type use the wider type
(which are also less likely to legalize). This can be avoided by
targets specifying legalization actions on type 1 earlier than for
type 0.

llvm-svn: 353455
 2019-02-07 19:37:44 +00:00
Matt Arsenault
d914189a2e AMDGPU/GlobalISel: Restrict g_implicit_def legality 
llvm-svn: 353452
 2019-02-07 19:10:15 +00:00
Matt Arsenault
c0f7569aab AMDGPU/GlobalISel: Legalize fsqrt 
llvm-svn: 353438
 2019-02-07 18:14:39 +00:00
Matt Arsenault
93fdec739b AMDGPU/GlobalISel: Legalize some f16 operations 
llvm-svn: 353436
 2019-02-07 18:03:11 +00:00
Matt Arsenault
c83b82363c GlobalISel: Implement fewerElementsVector for shifts 
Introduce a new function which handles instructions with multiple type
indices, but have the same number of vector elements.

Also legalize v2s16 shifts when applicable.

llvm-svn: 353432
 2019-02-07 17:38:00 +00:00
Matt Arsenault
91be65be65 GlobalISel: Try to make legalize rules more useful for vectors 
Mostly keep the existing functions on scalars, but add versions which
also operate based on the vector element size.

llvm-svn: 353430
 2019-02-07 17:25:51 +00:00
Matt Arsenault
10547230f3 AMDGPU/GlobalISel: Legalize select for v4s16 
Also add some more select tests to help show future legalization
changes.

llvm-svn: 353045
 2019-02-04 14:04:52 +00:00
Fangrui Song
b21ed3c57a [AMDGPU] Fix -Wunused-variable after rL352978 
llvm-svn: 352982
 2019-02-03 03:51:52 +00:00
Matt Arsenault
888aa5dedd GlobalISel: Implement widenScalar for G_UNMERGE_VALUES 
For the scalar case only.

Also move the similar G_MERGE_VALUES handling to a separate function
and cleanup to make them look more similar.

llvm-svn: 352979
 2019-02-03 00:07:33 +00:00
Matt Arsenault
0e5d856eb8 GlobalISel: Implement widenScalar for G_EXTRACT vector sources 
Handle the basic element extract case.

llvm-svn: 352978
 2019-02-02 23:56:00 +00:00
Matt Arsenault
eb2603cfb2 AMDGPU/GlobalISel: Avoid reporting illegal extloads as legal 
This avoids breaking a test in a future commit.

llvm-svn: 352977
 2019-02-02 23:39:13 +00:00
Matt Arsenault
58f9d3df97 AMDGPU/GlobalISel: Legalize icmp for pointer types 
llvm-svn: 352976
 2019-02-02 23:35:15 +00:00
Matt Arsenault
2065c94dd3 AMDGPU/GlobalISel: Legalize constant for pointer types 
llvm-svn: 352975
 2019-02-02 23:33:49 +00:00
Matt Arsenault
2491f82679 AMDGPU/GlobalISel: Legalize select for pointer types 
llvm-svn: 352974
 2019-02-02 23:31:50 +00:00
Matt Arsenault
cbaada6bc1 GlobalISel: Legalization for inttoptr/ptrtoint 
llvm-svn: 352973
 2019-02-02 23:29:55 +00:00
Matt Arsenault
c7bce739ad GlobalISel: Handle odd splits in fewerElementsVector for load/store 
llvm-svn: 352720
 2019-01-31 02:46:05 +00:00
Matt Arsenault
d1bfc8d0c3 GlobalISel: Implement narrowScalar for bswap 
llvm-svn: 352719
 2019-01-31 02:34:03 +00:00
Matt Arsenault
d5684f76e0 GlobalISel: Allow bitcount ops to have different result type 
For AMDGPU the result is always 32-bit for 64-bit inputs.

llvm-svn: 352717
 2019-01-31 02:09:57 +00:00
Matt Arsenault
dc6c78596b GlobalISel: Implement fewerElementsVector for select 
llvm-svn: 352601
 2019-01-30 04:19:31 +00:00
Matt Arsenault
f6cab16258 AMDGPU/GlobalISel: Fix clamping shifts with 16-bit insts 
llvm-svn: 352599
 2019-01-30 03:36:25 +00:00
Matt Arsenault
045bc9a4a6 GlobalISel: Support narrowScalar for uneven loads 
llvm-svn: 352594
 2019-01-30 02:35:38 +00:00
Matt Arsenault
d8d193d5e2 GlobalISel: Partially implement widenScalar for MERGE_VALUES 
llvm-svn: 352560
 2019-01-29 23:17:35 +00:00
Matt Arsenault
18619afe1d GlobalISel: Fix narrowScalar for load/store with different mem size 
This was ignoring the memory size, and producing multiple loads/stores
if the operand size was different from the memory size.

I assume this is the intent of not having an explicit G_ANYEXTLOAD
(although I think that would probably be better).

llvm-svn: 352523
 2019-01-29 18:13:02 +00:00
Matt Arsenault
211e89d4dd GlobalISel: Implement narrowScalar for mul 
llvm-svn: 352300
 2019-01-27 00:52:51 +00:00
Matt Arsenault
2e5f900849 GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_round 
llvm-svn: 352298
 2019-01-27 00:12:21 +00:00
Matt Arsenault
ded2f82662 AMDGPU/GlobalISel: Use scalarize instead of clampMaxNumElements 
llvm-svn: 352297
 2019-01-26 23:54:53 +00:00
Matt Arsenault
26a6c74fbe AMDGPU/GlobalISel: Legalize more bit ops 
llvm-svn: 352295
 2019-01-26 23:47:07 +00:00
Matt Arsenault
4d47594fc5 AMDGPU/GlobalISel: Widen small uaddo/usubo 
llvm-svn: 352294
 2019-01-26 23:44:51 +00:00
Matt Arsenault
3b9a82ff2c AMDGPU/GlobalISel: Remove leftover setAction 
Also move G_GEP actions together.

llvm-svn: 352168
 2019-01-25 04:54:00 +00:00
Matt Arsenault
3e08b772b3 AMDGPU/GlobalISel: Scalarize add/sub 
llvm-svn: 352167
 2019-01-25 04:53:57 +00:00
Matt Arsenault
e6cebd0d69 GlobalISel: fewerElementsVector for more cast types 
llvm-svn: 352166
 2019-01-25 04:37:33 +00:00
Matt Arsenault
95fd95cfe0 GlobalISel: fewerElementsVector for a few more trivial ops 
llvm-svn: 352165
 2019-01-25 04:03:38 +00:00
Matt Arsenault
5d622fbcc1 AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mul 
llvm-svn: 352162
 2019-01-25 03:23:04 +00:00
Matt Arsenault
1b1e685f10 GlobalISel: Support fewerElementsVector for icmp/fcmp 
Also legalize 64-bit compares for AMDGPU

llvm-svn: 352157
 2019-01-25 02:59:34 +00:00
Matt Arsenault
ca676343a9 GlobalISel: Implement fewerElementsVector for extensions 
llvm-svn: 352155
 2019-01-25 02:36:32 +00:00
Matt Arsenault
990f507704 GlobalISel: Add convenience mutatations to scalarize 
llvm-svn: 352143
 2019-01-25 00:51:00 +00:00
Matt Arsenault
4c5e8f51e7 AMDGPU/GlobalISel: Start selectively legalizing 16-bit operations 
It might be a bit nicer to use the fancy .legalIf and co. predicates,
but this was requiring more boilerplate and disables the coverage
assertions.

llvm-svn: 351886
 2019-01-22 22:00:19 +00:00
Matt Arsenault
736cfa9ffb AMDGPU/GlobalISel: Handle legality/regbanks for 32/64-bit shifts 
llvm-svn: 351884
 2019-01-22 21:51:38 +00:00
Matt Arsenault
30989e492b GlobalISel: Allow shift amount to be a different type 
For AMDGPU the shift amount is never 64-bit, and
this needs to use a 32-bit shift.

X86 uses i8, but seemed to be hacking around this before.

llvm-svn: 351882
 2019-01-22 21:42:11 +00:00
Matt Arsenault
6378629609 GlobalISel: Implement widen for extract_vector_elt elt type 
llvm-svn: 351871
 2019-01-22 20:38:15 +00:00
Matt Arsenault
aebb2ee036 GlobalISel: Implement fewerElementsVector for basic FP ops 
llvm-svn: 351866
 2019-01-22 20:14:29 +00:00
Matt Arsenault
41a8bee93b AMDGPU/GlobalISel: Remove vectors from legal constant types 
llvm-svn: 351859
 2019-01-22 19:04:51 +00:00
Matt Arsenault
6614f852b6 GlobalISel: Support narrowing zextload/sextload 
llvm-svn: 351856
 2019-01-22 19:02:10 +00:00
Matt Arsenault
fb67164ebc AMDGPU/GlobalISel: Legalize more fp<->int conversions 
llvm-svn: 351767
 2019-01-22 00:20:17 +00:00
Matt Arsenault
7ac79ed8f0 AMDGPU: Legalize more bitcasts 
llvm-svn: 351700
 2019-01-20 19:45:18 +00:00
Matt Arsenault
46ffe68d77 AMDGPU/GlobalISel: Really legalize exts from i1 
There is a combine that was hiding these tests
not actually testing what they should be, although
they were producing the expected end result.

llvm-svn: 351698
 2019-01-20 19:28:20 +00:00