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61145 Commits

Author SHA1 Message Date
Kenneth Uildriks
1850444000 Partial specialization was not checking the callsite to make sure it was using the same constants as the specialization, leading to calls to the wrong specialization. Patch by Takumi Nakamura\! 
llvm-svn: 105528
 2010-06-05 14:50:21 +00:00
Duncan Sands
e4f45cc88f This bug is also present in MSVC10. Requested by Elrood on IRC. 
llvm-svn: 105527
 2010-06-05 12:40:43 +00:00
Chris Lattner
fdd2614330 revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
594fa26317 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00
Bruno Cardoso Lopes
c4f614870f Teach tablegen to support 'defm' inside multiclasses. 
llvm-svn: 105519
 2010-06-05 02:11:52 +00:00
Dan Gohman
0501b03242 Make MachineFunctionPass::createPrinterPass private, as no subclasses 
should be calling it.

llvm-svn: 105517
 2010-06-05 01:19:12 +00:00
Dale Johannesen
81ef35b3ca Improvements to tail call code. No functional effect 
unless using -arm-tail-calls.

llvm-svn: 105515
 2010-06-05 00:51:39 +00:00
Dan Gohman
520913cf9e getFoldedOffsetOf no longer does anything special with vector types. 
llvm-svn: 105514
 2010-06-05 00:47:34 +00:00
Dan Gohman
8c292adba4 No need to special-case structs here; structs are first-class now. 
llvm-svn: 105513
 2010-06-05 00:42:29 +00:00
Stuart Hastings
3ca391027f Revert 105492 & 105493 due to a testcase regression. Radar 7424645. 
llvm-svn: 105511
 2010-06-05 00:39:29 +00:00
Dan Gohman
bbfb6aca92 LSR needs to remember inserted instructions even in postinc mode, because 
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

llvm-svn: 105510
 2010-06-05 00:33:07 +00:00
Dale Johannesen
df1a7f83bf Fix some liveout handling related to tail calls, see comments. 
I don't think this ever resulted in problems on x86, but it
would on ARM.

llvm-svn: 105509
 2010-06-05 00:30:45 +00:00
Dan Gohman
d7910a805d Implement operator== and operator!= for SetVector. 
llvm-svn: 105508
 2010-06-05 00:26:02 +00:00
Devang Patel
3eed2cf587 test case for r105504. 
Radar 8055687.

llvm-svn: 105505
 2010-06-04 23:47:41 +00:00
Evan Cheng
a03e6f85fe Re-apply 105308 with fix. 
llvm-svn: 105502
 2010-06-04 23:28:13 +00:00
Dan Gohman
67b4403101 Don't track users of undef values; they aren't interesting for 
register pressure.

llvm-svn: 105501
 2010-06-04 23:16:05 +00:00
Jim Grosbach
a1e08fb256 Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940 
llvm-svn: 105498
 2010-06-04 23:01:26 +00:00
Nate Begeman
7090e5be2b Handle multi-vector returns and args. 
llvm-svn: 105496
 2010-06-04 22:53:30 +00:00
Devang Patel
e89b759501 Update docs to reflect new DISubprogram elements. 
llvm-svn: 105495
 2010-06-04 22:49:55 +00:00
Stuart Hastings
7c015988fe Support for nested functions/classes in debug output. Radar 7424645. 
llvm-svn: 105492
 2010-06-04 22:36:03 +00:00
Devang Patel
36da24b546 Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info. 
llvm-svn: 105490
 2010-06-04 22:27:30 +00:00
Nate Begeman
0d081df3f2 Additional fixes to BuiltinsARM.def generator, on to clang codegen. 
llvm-svn: 105488
 2010-06-04 21:36:00 +00:00
Dale Johannesen
065d6fd537 More tail call removal. 
llvm-svn: 105485
 2010-06-04 21:14:24 +00:00
Jim Grosbach
50d229e6b3 Skip dbg_value instructions when scanning instructions in register scavenging. 
llvm-svn: 105481
 2010-06-04 20:18:30 +00:00
Dan Gohman
538b413ccb Fix normalization and de-normalization of non-affine SCEVs. 
llvm-svn: 105480
 2010-06-04 19:16:34 +00:00
Jakob Stoklund Olesen
864827afb0 Keep track of the call instructions whose clobber lists were skipped during fast 
register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

llvm-svn: 105473
 2010-06-04 18:08:29 +00:00
Dale Johannesen
d1b9311afa More thoroughly disable tails calls by default. 
8060143, although this doesn't fix the real problem with tail call.

llvm-svn: 105472
 2010-06-04 18:04:24 +00:00
Jim Grosbach
3548803f62 Another fix to prevent debug info from affecting codegen. rdar://7797940 
llvm-svn: 105470
 2010-06-04 17:57:34 +00:00
Nate Begeman
878bdccea6 Progress on generating BuiltinsARM.def, still some duplicates to work out. 
llvm-svn: 105461
 2010-06-04 07:11:25 +00:00
Nate Begeman
1ca8dba557 BuiltinsARM.def emitter, still needs a substantial bit of tweaking to lighten the load on clang. 
llvm-svn: 105456
 2010-06-04 01:26:15 +00:00
Jim Grosbach
4e5e6a8973 more dbg_value adjustments so debug info doesn't affect codegen 
llvm-svn: 105454
 2010-06-04 01:23:30 +00:00
Mon P Wang
622cdd2297 Fixed a bug during widening where we would avoid legalizing a node. When we 
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453
 2010-06-04 01:20:10 +00:00
Dale Johannesen
b3780b1103 Remove more tail calls. 
llvm-svn: 105450
 2010-06-04 01:01:24 +00:00
Dale Johannesen
e7b392dca9 Remove a tail call, and move some CHECKs to the 
functions where they belong.

llvm-svn: 105449
 2010-06-04 01:01:04 +00:00
Nate Begeman
03d6e4961c Mangle __builtin_neon_* names appropriately. 
Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

llvm-svn: 105443
 2010-06-04 00:21:41 +00:00
Dan Gohman
ae8bb42f5b No need to special-case structs here; structs are first-class now. 
llvm-svn: 105442
 2010-06-04 00:18:06 +00:00
Jim Grosbach
1bcdf32d22 fix typo 
llvm-svn: 105441
 2010-06-04 00:15:00 +00:00
Dan Gohman
8fdda8a655 This test doesn't need the ssp attribute. 
llvm-svn: 105440
 2010-06-04 00:14:48 +00:00
Bob Wilson
d8a9a04739 For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and 
VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

llvm-svn: 105439
 2010-06-04 00:04:02 +00:00
Dale Johannesen
e288fee959 Remove tail call. A tail call version will follow. 
llvm-svn: 105438
 2010-06-04 00:03:37 +00:00
Bob Wilson
a733daf18c Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs. 
Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass.  Some of
these constraints can be relaxed with a bit more work.  Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.

llvm-svn: 105437
 2010-06-03 23:53:58 +00:00
Jim Grosbach
01edd68225 Cleanup 80-column and trim trailing whitespace 
llvm-svn: 105435
 2010-06-03 23:49:57 +00:00
Jim Grosbach
b30b81edb6 Teach the ARM load-store optimizer to deal with dbg_value instructions. 
llvm-svn: 105427
 2010-06-03 22:41:15 +00:00
Dale Johannesen
9f71f7f70c Remove tail call to preserve this test. A tail 
call version will follow.

llvm-svn: 105422
 2010-06-03 21:57:48 +00:00
Dale Johannesen
41528aeb0b Make this test not use tail calls. A tail call 
version will follow.

llvm-svn: 105419
 2010-06-03 21:53:01 +00:00
Nate Begeman
64b76bd4f7 Add some additional capabilities to the neon emitter 
llvm-svn: 105416
 2010-06-03 21:35:22 +00:00
Rafael Espindola
8fb957e5cb Add a emit-llvm option to the plugin and make the path argument to also-emit-llvm optional. 
llvm-svn: 105414
 2010-06-03 21:11:20 +00:00
Dale Johannesen
d679ff7330 Early implementation of tail call for ARM. 
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413
 2010-06-03 21:09:53 +00:00
Dan Gohman
d83e3e7750 Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It 
needs to demand the high bits because it's asserting that they're zero.

llvm-svn: 105406
 2010-06-03 20:21:33 +00:00
Bob Wilson
30093b5d8b Revert 105308. 
llvm-svn: 105399
 2010-06-03 18:28:31 +00:00