501 Commits

Author SHA1 Message Date
Mark de Wever
cbaa3597aa Reland "[CMake] Bumps minimum version to 3.20.0.
This reverts commit d763c6e5e2d0a6b34097aa7dabca31e9aff9b0b6.

Adds the patch by @hans from
https://github.com/llvm/llvm-project/issues/62719
This patch fixes the Windows build.

d763c6e5e2d0a6b34097aa7dabca31e9aff9b0b6 reverted the reviews

D144509 [CMake] Bumps minimum version to 3.20.0.

This partly undoes D137724.

This change has been discussed on discourse
https://discourse.llvm.org/t/rfc-upgrading-llvms-minimum-required-cmake-version/66193

Note this does not remove work-arounds for older CMake versions, that
will be done in followup patches.

D150532 [OpenMP] Compile assembly files as ASM, not C

Since CMake 3.20, CMake explicitly passes "-x c" (or equivalent)
when compiling a file which has been set as having the language
C. This behaviour change only takes place if "cmake_minimum_required"
is set to 3.20 or newer, or if the policy CMP0119 is set to new.

Attempting to compile assembly files with "-x c" fails, however
this is workarounded in many cases, as OpenMP overrides this with
"-x assembler-with-cpp", however this is only added for non-Windows
targets.

Thus, after increasing cmake_minimum_required to 3.20, this breaks
compiling the GNU assembly for Windows targets; the GNU assembly is
used for ARM and AArch64 Windows targets when building with Clang.
This patch unbreaks that.

D150688 [cmake] Set CMP0091 to fix Windows builds after the cmake_minimum_required bump

The build uses other mechanism to select the runtime.

Fixes #62719

Reviewed By: #libc, Mordante

Differential Revision: https://reviews.llvm.org/D151344
2023-05-27 12:51:21 +02:00
Alex Bradbury
a1455de74d [RISCV][MC] Add support for experimental Zvfbfwma extension
Provides MC layer support for Zvfbfwma: vector BF16 widening mul-add.

As currently specified, Zvfbfwma does not appear to have a dependency on
Zvfbfmin or Zfbfmin.

Differential Revision: https://reviews.llvm.org/D147612
2023-05-19 15:37:26 +01:00
Alex Bradbury
b18a819664 [RISCV][MC] Add support for experimental Zvfbfmin extension
Provides MC layer support for Zfbfmin: vector BF16 conversions.

Zvfbfmin does not appear to have a dependency on Zfbfmin as currently
specified.

Differential Revision: https://reviews.llvm.org/D147611
2023-05-19 15:26:25 +01:00
Alex Bradbury
35ff5eba16 [RISCV][MC] Add support for experimental Zfbfmin extension
Provides MC layer support for Zfbfmin: scalar BF16 conversions.

As documented, this extension includes FLH, FSH, FMV.H.X, and FMH.X.H as
defined in Zfh/Zfhmin, but doesn't require either extension.

No Zfbfinxmin has been defined (though you would expect one in the
future, for symmetry with Zfhinxmin). See issue
https://github.com/riscv/riscv-bfloat16/issues/27.

Differential Revision: https://reviews.llvm.org/D147610
2023-05-19 15:17:56 +01:00
Aaron Ballman
53b6657043 Fix LLVM Sphinx build
Addresses the issue found in:
https://lab.llvm.org/buildbot/#/builders/30/builds/35298
2023-05-18 15:57:56 -04:00
Anders Waldenborg
298002916c [bindings] Remove LLVM python bindings
The LLVM python bindings are defunct.

They have not seen any substantial active development since 2014.

The version number, which is used to find the libLLVM-NN.so library, has
not been updated since LLVM 10.0 (2019) (and even then they were
probably mostly broken)

After fixing the version number to be able to run them at all, a large
number of tests in the test suite fails.

Already in 2017 the removal was discussed:
 https://discourse.llvm.org/t/is-anyone-using-still-using-the-python-bindings/46063
 https://lists.llvm.org/pipermail/llvm-dev/2017-August/116857.html

There exist external projects providing python bindings for LLVM, e.g:
 https://github.com/numba/llvmlite

Differential Revision: https://reviews.llvm.org/D150642
2023-05-18 21:40:22 +02:00
Nico Weber
d763c6e5e2 Revert "Reland "[CMake] Bumps minimum version to 3.20.0.""
This reverts commit 65429b9af6a2c99d340ab2dcddd41dab201f399c.

Broke several projects, see https://reviews.llvm.org/D144509#4347562 onwards.

Also reverts follow-up commit "[OpenMP] Compile assembly files as ASM, not C"

This reverts commit 4072c8aee4c89c4457f4f30d01dc9bb4dfa52559.

Also reverts fix attempt  "[cmake] Set CMP0091 to fix Windows builds after the cmake_minimum_required bump"

This reverts commit 7d47dac5f828efd1d378ba44a97559114f00fb64.
2023-05-17 10:53:33 -04:00
Weining Lu
2cf0314029 [LoongArch] Move lp64s out of the unimplemented calling conv list
lp64s is same as lp64d execpt that floating point arguments and return
values are always passed via GPRs or stack which means `UseGPRForFloat`
is always `true` in `CC_LoongArch` for lp64s.

One motivation of this change is to build linux which uses
`-msoft-float` and `-mabi=lp64s` [1].

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/Makefile?h=v6.4-rc1#n49

Reviewed By: xen0n, hev

Differential Revision: https://reviews.llvm.org/D150417
2023-05-16 21:09:31 +08:00
Mark de Wever
65429b9af6 Reland "[CMake] Bumps minimum version to 3.20.0."
The owner of the last two failing buildbots updated CMake.

This reverts commit e8e8707b4aa6e4cc04c0cffb2de01d2de71165fc.
2023-05-13 11:42:25 +02:00
Craig Topper
728b8a1398 [RISCV] Make zve32f imply F and zve64d imply D.
The 1.0 vector spec PDF has text that says that Zve32f is compatible
with F or Zfinx and that Zve64d is compatible with D and Zdinx.
The references to *inx were removed from the spec in the github repository in
October 2021. The 1.0 pdf was made in September 2021.

Relevant commit 6fedb869e2

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D150021
2023-05-06 23:17:16 -07:00
Mark de Wever
e8e8707b4a Revert "Reland "[CMake] Bumps minimum version to 3.20.0.""
Unfortunatly not all buildbots are updated.

This reverts commit ffb807ab5375b3f78df198dc5d4302b3b552242f.
2023-05-06 17:03:56 +02:00
Mark de Wever
ffb807ab53 Reland "[CMake] Bumps minimum version to 3.20.0."
All build bots should be updated now.

This reverts commit 44d38022ab29a3156349602733b3459df5beef93.
2023-05-06 11:43:02 +02:00
Michael Maitland
839469436a [RISCV] Add sifive-x280 processor with all of its extensions
Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710
2023-05-05 10:02:28 -07:00
Michael Maitland
6e7ca6839d Revert "[RISCV] Add sifive-x280 processor with all of its extensions"
Test still not working...

This reverts commit a11dfd0fe6b1c38495f7de9858a2d1839d2902b9.
2023-05-05 09:03:06 -07:00
Michael Maitland
a11dfd0fe6 [RISCV] Add sifive-x280 processor with all of its extensions
Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710
2023-05-05 08:47:57 -07:00
Michael Maitland
d6bd4ea354 Revert "[RISCV] Add sifive-x280 processor with all of its extensions"
This commit causes tests to fail.

This reverts commit 55e196e7718c543b4492f2949c13de003a4ba443.
2023-05-05 08:20:18 -07:00
Michael Maitland
55e196e771 [RISCV] Add sifive-x280 processor with all of its extensions
Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710
2023-05-05 07:55:07 -07:00
Nick Desaulniers
3e3c6f24ff Revert "[Demangle] make llvm::demangle take std::string_view rather than const std::string&"
This reverts commit c117c2c8ba4afd45a006043ec6dd858652b2ffcc.

itaniumDemangle calls std::strlen with the results of
std::string_view::data() which may not be NUL-terminated. This causes
lld/test/wasm/why-extract.s  to fail when "expensive checks" are enabled
via -DLLVM_ENABLE_EXPENSIVE_CHECKS=ON. See D149675 for further
discussion. Back this out until the individual demanglers are converted
to use std::string_view.
2023-05-02 15:54:09 -07:00
Nick Desaulniers
c117c2c8ba [Demangle] make llvm::demangle take std::string_view rather than const std::string&
As suggested by @erichkeane in
https://reviews.llvm.org/D141451#inline-1429549

There's potential for a lot more cleanups around these APIs. This is
just a start.

Callers need to be more careful about sub-expressions producing strings
that don't outlast the expression using ``llvm::demangle``. Add a
release note.

Reviewed By: MaskRay, #lld-macho

Differential Revision: https://reviews.llvm.org/D149104
2023-05-02 11:20:15 -07:00
Craig Topper
fa42e7b6bc [RISCV] Merge RISCV::parseCPUKind and RISCV::checkCPUKind.
Similar for RISCV::parseTuneCPU and RISCV::checkTuneCPUKind.

This makes the CPUKind enum no longer part of the API. It wasn't
providing much value. It was only used to pass between the two
functions.

By removing it, we can remove a dependency on a tablegen generated
file from the RISCVTargetParser.h file. Then we can remove a
dependency from several CMakeLists.txt.
2023-05-01 13:00:05 -07:00
Daniel Kiss
d75e70d7ae [AArch64] Add preserve_all calling convention.
Clang accepts preserve_all for AArch64 while it is missing form the backed.

Fixes #58145

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D135652
2023-04-28 14:55:38 +02:00
Craig Topper
f0c36dc964 [RISCV] Remove CSR names that are not in Privileged Specification 1.12.
These are from the N extension (User-Level Interrupts) which did
not make it into 1.12 of the Privileged Specification.

D117653 also tried to remove some of these, but it was never reviewed.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D149278
2023-04-26 13:35:20 -07:00
Alex Bradbury
3e4000034a [doc][RISCV] Add missed release note about vector crypto extension update
I meant to fold this into cb7dffdc9a83f400410657431bda14e79f6e0176 but
failed to do so.
2023-04-20 18:30:53 +01:00
Alex Bradbury
2a5661c841 [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description
As of
1f03818281
in the riscv-isa-manual, Zfa is at version 0.2. Reviewing the commit
history for
zfa.tex
<https://github.com/riscv/riscv-isa-manual/commits/master/src/zfa.tex>
there are no relevant changes since 0.1. As such, we can simply
increment the version number.

This change also removes the claim in RISCVUsage that we implement a
"subset of" Zfa, as I believe this is no longer true. That sentence
previously incorrectly claimed we didn't implement fli.{h,s,d} (I
[corrected this a couple of weeks
ago](https://reviews.llvm.org/rG3d969191b277)) but I think should have
removed the "subset of" wording too.

As was noted during the review, we never added Zfa to the release notes.
This is corrected in this patch.

Differential Revision: https://reviews.llvm.org/D148634
2023-04-19 06:27:35 +01:00
Mark de Wever
44d38022ab Revert "Revert "Revert "[CMake] Bumps minimum version to 3.20.0."""
This reverts commit 1ef4c3c859728008cf707cad8d67f45ae5070ae1.

Two buildbots still haven't been updated.
2023-04-15 20:12:24 +02:00
Mark de Wever
1ef4c3c859 Revert "Revert "[CMake] Bumps minimum version to 3.20.0.""
This reverts commit 92523a35a827539db8557bbc3ecab7f9ea3f6ade.

Reland to see whether CIs are updated.
2023-04-15 13:12:04 +02:00
Nikita Popov
62ef97e063 [llvm-c] Remove PassRegistry and initialization APIs
Remove C APIs for interacting with PassRegistry and pass
initialization. These are legacy PM concepts, and are no longer
relevant for the new pass manager.

Calls to these initialization functions can simply be dropped.

Differential Revision: https://reviews.llvm.org/D145043
2023-04-14 12:12:48 +02:00
David Spickett
e07a421dd5 [lldb] Show register fields using bitfield struct types
This change uses the information from target.xml sent by
the GDB stub to produce C types that we can use to print
register fields.

lldb-server *does not* produce this information yet. This will
only work with GDB stubs that do. gdbserver or qemu
are 2 I know of. Testing is added that uses a mocked lldb-server.
```
(lldb) register read cpsr x0 fpcr fpsr x1
    cpsr = 0x60001000
         = (N = 0, Z = 1, C = 1, V = 0, TCO = 0, DIT = 0, UAO = 0, PAN = 0, SS = 0, IL = 0, SSBS = 1, BTYPE = 0, D = 0, A = 0, I = 0, F = 0, nRW = 0, EL = 0, SP = 0)
```

Only "register read" will display fields, and only when
we are not printing a register block.

For example, cpsr is a 32 bit register. Using the target's scratch type
system we construct a type:
```
struct __attribute__((__packed__)) cpsr {
  uint32_t N : 1;
  uint32_t Z : 1;
  ...
  uint32_t EL : 2;
  uint32_t SP : 1;
};
```

If this register had unallocated bits in it, those would
have been filled in by RegisterFlags as anonymous fields.
A new option "SetChildPrintingDecider" is added so we
can disable printing those.

Important things about this type:
* It is packed so that sizeof(struct cpsr) == sizeof(the real register).
  (this will hold for all flags types we create)
* Each field has the same storage type, which is the same as the type
  of the raw register value. This prevents fields being spilt over
  into more storage units, as is allowed by most ABIs.
* Each bitfield size matches that of its register field.
* The most significant field is first.

The last point is required because the most significant bit (MSB)
being on the left/top of a print out matches what you'd expect to
see in an architecture manual. In addition, having lldb print a
different field order on big/little endian hosts is not acceptable.

As a consequence, if the target is little endian we have to
reverse the order of the fields in the value. The value of each field
remains the same. For example 0b01 doesn't become 0b10, it just shifts
up or down.

This is needed because clang's type system assumes that for a struct
like the one above, the least significant bit (LSB) will be first
for a little endian target. We need the MSB to be first.

Finally, if lldb's host is a different endian to the target we have
to byte swap the host endian value to match the endian of the target's
typesystem.

| Host Endian | Target Endian | Field Order Swap | Byte Order Swap |
|-------------|---------------|------------------|-----------------|
| Little      | Little        | Yes              | No              |
| Big         | Little        | Yes              | Yes             |
| Little      | Big           | No               | Yes             |
| Big         | Big           | No               | No              |

Testing was done as follows:
* Little -> Little
  * LE AArch64 native debug.
* Big -> Little
  * s390x lldb running under QEMU, connected to LE AArch64 target.
* Little -> Big
  * LE AArch64 lldb connected to QEMU's GDB stub, which is running
    an s390x program.
* Big -> Big
 * s390x lldb running under QEMU, connected to another QEMU's GDB
   stub, which is running an s390x program.

As we are not allowed to link core code to plugins directly,
I have added a new plugin RegisterTypeBuilder. There is one implementation
of this, RegisterTypeBuilderClang, which uses TypeSystemClang to build
the CompilerType from the register fields.

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D145580
2023-04-13 13:04:34 +00:00
Paul Kirth
aa1d2693c2 [CodeGen][RISCV] Change Shadow Call Stack Register to X3
ShadowCallStack implementation uses s2 register on RISC-V, but that
choice is problematic for reasons described in:

https://lists.riscv.org/g/sig-toolchains/message/544,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370, and
https://github.com/google/android-riscv64/issues/72

The concern over the register choice was also brought up in
https://reviews.llvm.org/D84414.

https://reviews.llvm.org/D84414#2228666 said:

```
  "If the register choice is the only concern about this work, then I think
  we can probably land it as-is and fixup the register choice if we see
  major drawbacks later. Yes, it's an ABI issue, but on the other hand the
  shadow call stack is not a standard ABI anyway.""
```

Since we have now found a sufficient reason to fixup the register
choice, we should go ahead and update the implementation. We propose
using x3(gp) which is now the platform register in the RISC-V ABI.

Reviewed By: asb, hiraditya, mcgrathr, craig.topper

Differential Revision: https://reviews.llvm.org/D146463
2023-04-12 21:06:22 +00:00
Nelson Chu
0b9a620b83 [RISCV] Support assembler and dis-assembler for VCIX extension.
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf

Differential Revision: https://reviews.llvm.org/D144530
2023-04-09 20:41:01 -07:00
Michael Buch
8b0033e58a [ReleaseNotes] DebugInfo: preferred_name attribute changes
Describes changes made in D145803.

Differential Revision: https://reviews.llvm.org/D147695
2023-04-07 01:37:37 +01:00
Aaron Ballman
ceacb32524 Fix LLVM sphinx build
This addresses issues found by:
https://lab.llvm.org/buildbot/#/builders/30/builds/33698
2023-04-05 13:25:07 -04:00
Roy Sundahl
5f17ba1a38 [sanitizers] Simplify Explainer about dyld and weak overrides on Darwin. (NFC)
Presenting more than one way to satisfy the single-weak-ref requirement leads to
confusing messaging for the end user. Use the introduction of a single unused
weak variable as the preferred solution. This differential modifies D146745.

rdar://103453678

Reviewed By: yln, thetruestblue

Differential Revision: https://reviews.llvm.org/D147526
2023-04-05 10:04:29 -07:00
Archibald Elliott
0104305bc8 [NFC][AArch64] Late 2022 A-Profile Extension Release Notes 2023-04-04 11:39:41 +01:00
Roy Sundahl
f1c5c84ae1 [sanitizers] Explainer about dyld and weak overrides on Darwin. (NFC)
Explain in the release notes that the Darwin dynamic linker (dyld) requires
that at least one weak symbol be present in any mach-o file that defines an
intended override of a sanitizer dylib weak reference.

rdar://103453678

Reviewed By: thetruestblue

Differential Revision: https://reviews.llvm.org/D146745
2023-03-31 08:55:49 -07:00
Qiongsi Wu
f624372ccb [AIX][CodeGen] Renaming mroptr to xcoff-mroptr
This patch renames the `mroptr` option to `mxcoff-roptr` to indicate in the option itself that it is xcoff specific.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D147161
2023-03-31 10:09:48 -04:00
Craig Topper
dc90af501f [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
New versions I2.1, F2.2, D2.2 A2.1

Make F and Zfinx imply Zicsr.
Make G imply Zifencei.

This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly.

See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D147179
2023-03-30 15:28:44 -07:00
Alex Bradbury
d3291c692c [RISCV][MC] Add support for the experimental zicond extension
This patch adds the basic MC layer support for Zicond, based on
[1.0-rc1](https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1).
As with other extensions, if there are additional changes between
release candidates without incrementing the version number we won't be
able to reflect that in the version number. I believe we've previously
decided this is not a problem for extensions still considered
experimental (i.e. not yet ratified).

Differential Revision: https://reviews.llvm.org/D146946
2023-03-29 12:17:50 +01:00
Wael Yehia
256914bf1c [AIX] Update release notes regarding -mxcoff-build-id and the profile runtime 2023-03-28 14:53:12 +00:00
Qiongsi Wu
4f9929add5 [AIX][CodeGen] Storage Locations for Constant Pointers
This patch adds an `llc` option `-mroptr` to specify storage locations for constant pointers on AIX.

When the `-mroptr` option is specified, constant pointers, virtual function tables, and virtual type tables are placed in read-only storage. Otherwise, by default, pointers, virtual function tables, and virtual type tables are placed are placed in read/write storage.

https://reviews.llvm.org/D144190 enables the `-mroptr` option for `clang`.

Reviewed By: hubert.reinterpretcast, stephenpeckham, myhsu, MaskRay, serge-sans-paille

Differential Revision: https://reviews.llvm.org/D144189
2023-03-23 09:44:47 -04:00
Job Noorman
c39dd7c1db [RISCV][MC] Add support for RV64E
Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570
2023-03-23 12:32:25 +00:00
David Spickett
85bc498826 [LLDB] Show sub type of signals when debugging a core file
Previously we only looked at the si_signo field, so you got:
```
(lldb) bt
* thread #1, name = 'a.out.mte', stop reason = signal SIGSEGV
  * frame #0: 0x00000000004007f4
```
This patch adds si_code so we can show:
```
(lldb) bt
* thread #1, name = 'a.out.mte', stop reason = signal SIGSEGV: sync tag check fault
  * frame #0: 0x00000000004007f4
```

The order of errno and code was incorrect in ElfLinuxSigInfo::Parse.
It was the order that a "swapped" siginfo arch would use, which for Linux,
is only MIPS. We removed MIPS Linux support some time ago.

See:
fe15c26ee2/include/uapi/asm-generic/siginfo.h (L121)

A test is added using memory tagging faults. Which were the original
motivation for the changes.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D146045
2023-03-21 09:10:09 +00:00
Austin Kerbow
09f756c880 [AMDGPU] Add release note for ommited barrier waitcnt
Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D146353
2023-03-19 21:15:28 -07:00
Mark de Wever
d0398d3593 Revert "Reland "[CMake] Bumps minimum version to 3.20.0.""
This reverts commit a72165e5df59032cdd54dcb18155f2630d73abd1.

Some buildbots have not been updated yet.
2023-03-18 20:32:43 +01:00
Mark de Wever
a72165e5df Reland "[CMake] Bumps minimum version to 3.20.0."
This reverts commit 92523a35a827539db8557bbc3ecab7f9ea3f6ade.

Test whether all CI runners are updated.
2023-03-18 13:33:42 +01:00
Paul Kirth
93c1a5f3dd [llvm-readobj] Rename JSON Flag fields to be more consistent
Today the JSON uses `Value` and `RawValue` when printing `Flags`, when really
the `Value` field is always the name of an Enum variant, and `RawValue` is its
underlying numeric value. Similarly, we rename the `RawFlags` key to `Value`,
to match the new scheme. This also allows JSON parsing to use consistent logic
for `Flag` types.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D137091
2023-03-18 00:04:47 +00:00
Aaron Ballman
d73c51bfda Fix LLVM Sphinx build
This addresses the issue found by:
https://lab.llvm.org/buildbot/#/builders/30/builds/33006
2023-03-16 14:03:39 -04:00
Arthur Eubanks
a63270cda8 [docs] Mention removal of legacy optimization pipeline and inliner alloca merging
Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D146243
2023-03-16 10:48:06 -07:00
Nikita Popov
bbfb13a5ff [ConstExpr] Remove select constant expression
This removes the select constant expression, as part of
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179.
Uses of this expressions have already been removed in advance,
so this just removes related infrastructure and updates tests.

Differential Revision: https://reviews.llvm.org/D145382
2023-03-16 10:32:08 +01:00
Arthur Eubanks
9e0c2626f3 [llvm-c] Remove pointee support from LLVMGetElementType
Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D145717
2023-03-09 15:42:38 -08:00