5 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
4b111dd798 [AMDGPU] Fix VOPD dependency checks during combine
Check superreg/subreg defs of an instruction when checking for
dependencies. This may cause some regressions, but better be
safe than sorry. Changed tests are affected because of the
implicit-defs of the superregs.

Differential Revision: https://reviews.llvm.org/D152943
2023-06-15 11:16:33 -07:00
Benjamin Kramer
b6942a2880 [NFC] Hide implementation details in anonymous namespaces 2023-01-08 17:37:02 +01:00
Dmitry Preobrazhensky
96155bf44b [AMDGPU][GFX11][NFC] Refactor VOPD operands handling (part 2)
Rename interface functions and operands to make code clearer.

Differential Revision: https://reviews.llvm.org/D138133
2022-11-18 14:15:05 +03:00
Dmitry Preobrazhensky
1d1c7555e2 [AMDGPU][GFX11][NFC] Refactor VOPD handling in codegen
Differential Revision: https://reviews.llvm.org/D135084
2022-10-07 16:13:05 +03:00
Joe Nash
d1af09ad96 [AMDGPU] gfx11 Generate VOPD Instructions
We form VOPD  instructions in the GCNCreateVOPD pass by combining
back-to-back component instructions. There are strict register
constraints for creating a legal VOPD, namely that the matching operands
(e.g. src0x and src0y, src1x and src1y) must be in different register
banks. We add a PostRA scheduler
mutation to put possible VOPD components back-to-back.

Depends on D128442, D128270

Reviewed By: #amdgpu, rampitec

Differential Revision: https://reviews.llvm.org/D128656
2022-07-05 09:18:19 -04:00