13362 Commits

Author SHA1 Message Date
Rafael Espindola
ba0a6cabb8 Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.

llvm-svn: 154011
2012-04-04 12:51:34 +00:00
Craig Topper
4c7d995029 Remove default case from switch that was already covering all cases.
llvm-svn: 153996
2012-04-04 04:42:42 +00:00
Pete Cooper
e7bff68a5e Removed useless switch for default case when switch was covering all the enum values
llvm-svn: 153984
2012-04-04 00:53:04 +00:00
Pete Cooper
9511ec86f9 Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095>
llvm-svn: 153976
2012-04-03 22:57:55 +00:00
Pete Cooper
b98934cf72 Removed one last bad continue statement meant to be removed in r153914.
llvm-svn: 153975
2012-04-03 22:18:49 +00:00
Chad Rosier
2a02fe1bb2 Fix an issue in SimplifySetCC() specific to vector comparisons.
When folding X == X we need to check getBooleanContents() to determine if the
result is a vector of ones or a vector of negative ones. 

I tried creating a test case, but the problem seems to only be exposed on a
much older version of clang (around r144500).
rdar://10923049

llvm-svn: 153966
2012-04-03 20:11:24 +00:00
Eric Christopher
b81e2b403c Fix thinko check for number of operands to be the one that actually
might have more than 19 operands. Add a testcase to make sure I
never screw that up again.

Part of rdar://11026482

llvm-svn: 153961
2012-04-03 17:55:42 +00:00
Eric Christopher
34164196af Add a line number for the scope of the function (starting at the first
brace) so that we get more accurate line number information about the
declaration of a given function and the line where the function
first starts.

Part of rdar://11026482

llvm-svn: 153916
2012-04-03 00:43:49 +00:00
Pete Cooper
4f0dbb27d9 Fixes to r153903. Added missing explanation of behaviour when the VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created
llvm-svn: 153914
2012-04-03 00:28:46 +00:00
Pete Cooper
3ca96f9950 Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen
llvm-svn: 153906
2012-04-02 22:44:18 +00:00
Jakob Stoklund Olesen
291007b055 Allocate virtual registers in ascending order.
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.

Patch by Shamil Kurmangaleev!

llvm-svn: 153904
2012-04-02 22:30:39 +00:00
Pete Cooper
2bde2f42b1 Refactored the LiveRangeEdit interface so that MachineFunction, TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method.
llvm-svn: 153903
2012-04-02 22:22:53 +00:00
Owen Anderson
98f2c0c384 Add predicates for checking whether targets have free FNEG and FABS operations, and prevent the DAGCombiner from turning them into bitwise operations if they do.
llvm-svn: 153901
2012-04-02 22:10:29 +00:00
Lang Hames
aaafacd07e During two-address lowering, rescheduling an instruction does not untie
operands. Make TryInstructionTransform return false to reflect this.
Fixes PR11861.

llvm-svn: 153892
2012-04-02 19:58:43 +00:00
Eric Christopher
ad9fe8955a Turn on the accelerator tables for Darwin.
llvm-svn: 153880
2012-04-02 17:58:52 +00:00
Nadav Rotem
702f080767 Optimizing swizzles of complex shuffles may generate additional complex shuffles.
Do not try to optimize swizzles of shuffles if the source shuffle has more than
a single user, except when the source shuffle is also a swizzle.

llvm-svn: 153864
2012-04-02 07:11:12 +00:00
Craig Topper
54bfde79db Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
llvm-svn: 153860
2012-04-02 06:09:36 +00:00
Nadav Rotem
b078350872 This commit contains a few changes that had to go in together.
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
   (and also scalar_to_vector).

2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
   Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))

3. Optimize swizzles of shuffles:  shuff(shuff(x, y), undef) -> shuff(x, y).

4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.

Code which was previously compiled to this:

movd    (%rsi), %xmm0
movdqa  .LCPI0_0(%rip), %xmm2
pshufb  %xmm2, %xmm0
movd    (%rdi), %xmm1
pshufb  %xmm2, %xmm1
pxor    %xmm0, %xmm1
pshufb  .LCPI0_1(%rip), %xmm1
movd    %xmm1, (%rdi)
ret

Now compiles to this:

movl    (%rsi), %eax
xorl    %eax, (%rdi)
ret

llvm-svn: 153848
2012-04-01 19:31:22 +00:00
Lang Hames
652f21274f Fix typo.
llvm-svn: 153846
2012-04-01 19:27:25 +00:00
Andrew Trick
779b32a44e misched: Add finalizeScheduler to complete the target interface.
llvm-svn: 153827
2012-04-01 07:24:23 +00:00
Rafael Espindola
80c540e656 Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable
performance difference with any combination of -O0/-O2 /-g when compiling
gcc as a single compilation unit.

llvm-svn: 153817
2012-03-31 18:14:00 +00:00
Bill Wendling
9f829f1cc4 If we have a VLA that has a "use" in a metadata node that's then used
here but it has no other uses, then we have a problem. E.g.,

  int foo (const int *x) {
    char a[*x];
    return 0;
  }

If we assign 'a' a vreg and fast isel later on has to use the selection
DAG isel, it will want to copy the value to the vreg. However, there are
no uses, which goes counter to what selection DAG isel expects.
<rdar://problem/11134152>

llvm-svn: 153705
2012-03-30 00:02:55 +00:00
Eric Christopher
70e1bd8872 Add support for objc property decls according to the page at:
http://llvm.org/docs/SourceLevelDebugging.html#objcproperty

including type and DECL. Expand the metadata needed accordingly.

rdar://11144023

llvm-svn: 153639
2012-03-29 08:42:56 +00:00
Jakob Stoklund Olesen
c3e80cc885 Enable machine code verification in the entire code generator.
Some targets still mess up the liveness information, but that isn't
verified after MRI->invalidateLiveness().

The verifier can still check other useful things like register classes
and CFG, so it should be enabled after all passes.

llvm-svn: 153615
2012-03-28 23:54:28 +00:00
Jakob Stoklund Olesen
d1bd8fba13 Enable machine code verification after PreSched2 passes.
The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax the terminator checking in the machine code verifier so it can
handle the basic blocks created by if conversion.

llvm-svn: 153614
2012-03-28 23:31:15 +00:00
Jakob Stoklund Olesen
e433c68d7c Also verify after ExpandPostRAPseudos.
llvm-svn: 153599
2012-03-28 20:49:30 +00:00
Jakob Stoklund Olesen
341e06f8d5 Enable machine code verification after the late machine optimization passes.
Branch folding invalidates liveness and disables liveness verification
on some targets.

llvm-svn: 153597
2012-03-28 20:47:37 +00:00
Jakob Stoklund Olesen
b21df32cf5 Skip liveness verification when MRI->tracksLiveness() is false.
Extract the liveness verification into its own method.

This makes it possible to run the machine code verifier after liveness
information is no longer required to be valid.

llvm-svn: 153596
2012-03-28 20:47:35 +00:00
Jakob Stoklund Olesen
8e58c90f51 Allow removeLiveIn to be called with a register that isn't live-in.
This avoids the silly double search:

  if (isLiveIn(Reg))
    removeLiveIn(Reg);

llvm-svn: 153592
2012-03-28 20:11:42 +00:00
Pete Cooper
148ebb8802 Fixed commuteInstructions bug where if its called pre-regalloc the subreg indices weren't commuted
llvm-svn: 153579
2012-03-28 17:02:22 +00:00
Eric Christopher
24a6298512 More debug output.
llvm-svn: 153571
2012-03-28 07:34:36 +00:00
Eric Christopher
7285c7d51d Fix the output of the DW_TAG_friend tag to include DW_AT_friend
and not the rest of the member tag.

Fixes PR11695

llvm-svn: 153570
2012-03-28 07:34:31 +00:00
Lang Hames
5544bf1b8a Use a SmallVector and linear lookup instead of a DenseSet - SourceMap values
will always be tiny sets, so DenseSet is overkill (SmallSet won't work as we
need iteration support). 

llvm-svn: 153529
2012-03-27 19:10:45 +00:00
Eric Christopher
7ed2efca6a Use DW_AT_low_pc for a single entry point into a routine.
Fixes PR10105

llvm-svn: 153524
2012-03-27 18:35:54 +00:00
Jakob Stoklund Olesen
6c08534aff Print SSA and liveness tracking flags in MF::print().
llvm-svn: 153518
2012-03-27 17:17:16 +00:00
Jakob Stoklund Olesen
d1664a1571 Branch folding may invalidate liveness.
Branch folding can use a register scavenger to update liveness
information when required. Don't do that if liveness information is
already invalid.

llvm-svn: 153517
2012-03-27 17:06:09 +00:00
Chris Lattner
1cc25e8a40 fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)
llvm-svn: 153513
2012-03-27 16:27:21 +00:00
Jakob Stoklund Olesen
9c1ad5cb7d Add an MRI::tracksLiveness() flag.
Late optimization passes like branch folding and tail duplication can
transform the machine code in a way that makes it expensive to keep the
register liveness information up to date. There is a fuzzy line between
register allocation and late scheduling where the liveness information
degrades.

The MRI::tracksLiveness() flag makes the line clear: While true,
liveness information is accurate, and can be used for register
scavenging. Once the flag is false, liveness information is not
accurate, and can only be used as a hint.

Late passes generally don't need the liveness information, but they will
sometimes use the register scavenger to help update it. The scavenger
enforces strict correctness, and we have to spend a lot of code to
update register liveness that may never be used.

llvm-svn: 153511
2012-03-27 15:13:58 +00:00
Evan Cheng
7fede87349 Post-ra LICM should take care not to hoist an instruction that would clobber a
register that's read by the preheader terminator.

rdar://11095580

llvm-svn: 153492
2012-03-27 01:50:58 +00:00
Lang Hames
551662bf5d During MachineCopyPropagation a register may be the source operand of multiple
copies being considered for removal. Make sure to track all of the copies,
rather than just the most recent encountered, by holding a DenseSet instead of
an unsigned in SrcMap.

No test case - couldn't reduce something with a sane size.

llvm-svn: 153487
2012-03-27 00:44:47 +00:00
Lang Hames
95e021faf5 Add a debug option to dump PBQP graphs during register allocation.
llvm-svn: 153483
2012-03-26 23:07:23 +00:00
Eric Christopher
0925c62c74 Use the file in the inlined die rather than the compile unit for
backtrace locations.

Testcase forthcoming, but I wanted to get some testing here.

Should fix:

PR12323
PR12314
rdar://11091100

llvm-svn: 153471
2012-03-26 21:38:38 +00:00
Benjamin Kramer
3e6719c133 No need to do an expensive stable sort for a bunch of integers.
llvm-svn: 153438
2012-03-26 14:17:26 +00:00
Craig Topper
6e80c28017 Prune some includes and forward declarations.
llvm-svn: 153429
2012-03-26 06:58:25 +00:00
Eric Christopher
c1e2dcdb8a Add a debug statement.
llvm-svn: 153428
2012-03-26 06:10:32 +00:00
Hal Finkel
71c2ba3d2e Add the ability to promote legal integer VAARGs. This is required for the PPC64 SVR4 ABI.
llvm-svn: 153372
2012-03-24 03:53:52 +00:00
Jim Grosbach
4a2909ab0f Pretty-printing comments for literal floating point in .s files.
Dump the hex representation to the comment stream as well as the float
value.

llvm-svn: 153346
2012-03-23 23:06:47 +00:00
Lang Hames
45c6d21ae1 Add support for register masks to PBQP.
llvm-svn: 153341
2012-03-23 17:33:42 +00:00
Evan Cheng
8ab58a21a5 Source order scheduler should not preschedule nodes with multiple uses. rdar://11096639
llvm-svn: 153270
2012-03-22 19:31:17 +00:00
Evan Cheng
79f03e915d Assign node orders to target intrinsics which do not produce results. rdar://11096639
llvm-svn: 153269
2012-03-22 19:29:09 +00:00