83 Commits

Author SHA1 Message Date
Freddy Ye
97836bed63
Reland "[X86] Support -march=diamondrapids (#113881)" (#116564)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-18 10:40:32 +08:00
Freddy Ye
90e92239bd
Revert "[X86] Support -march=diamondrapids (#113881)" (#116563)
This reverts commit 826b845c9e97448395431be3e4e5da585bd98c5e.
2024-11-18 08:45:28 +08:00
Freddy Ye
826b845c9e
[X86] Support -march=diamondrapids (#113881)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-18 08:31:17 +08:00
tangaac
2283d50447
[LoongArch] add la v1.1 features for sys::getHostCPUFeatures (#115832)
Two features (i.e. `frecipe` and `lam-bh`) are added to
`sys.getHostCPUFeatures`. More features will be added in future.

In addition, this patch adds the features returned by
`sys.getHostCPUFeature` when `-march=native`.
2024-11-14 11:25:32 +08:00
Elvina Yakubova
133f8fa233
Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (#115467)
…eatures in cpu info

Relands #97749. Fixed test by adding additional checks for system linux
and target == host.
2024-11-13 09:10:56 +00:00
Malay Sanghi
f77101ea79
[X86][AMX] Support AMX-MOVRS (#115151)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-12 15:05:43 +08:00
Feng Zou
eddb79d56d
[X86][AMX] Support AMX-TF32 (#115625)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-11 15:24:18 +08:00
Phoebe Wang
8f4401374c
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
2024-11-09 13:26:10 +08:00
Alan Zhao
ff22515430
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070

Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
2024-11-08 16:15:02 -08:00
Phoebe Wang
58a17e1bbc
[X86][AMX] Support AMX-AVX512 (#114070) 2024-11-08 16:25:16 +08:00
Phoebe Wang
c72a751dab
[X86][AMX] Support AMX-TRANSPOSE (#113532)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-01 16:45:03 +08:00
Feng Zou
8127162427
[X86][AMX] Support AMX-FP8 (#113850)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-31 10:14:25 +08:00
Elvina Yakubova
80a09735ac
Revert "[clang][AArch64] Add getHostCPUFeatures to query for enabled … (#114066)
…features in cpu info (#97749)"

This reverts commit d732c0b13c55259177f2936516b6087d634078e0.

This is breaking buildbots
https://lab.llvm.org/buildbot/#/builders/190/builds/8413,
https://lab.llvm.org/buildbot/#/builders/56/builds/10880 and a few
others.
2024-10-29 14:43:01 +00:00
neildhickey
d732c0b13c
[clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (#97749)
Add getHostCPUFeatures into the AArch64 Target Parser to query the 
cpuinfo for the device in the case where we are compiling with 
-mcpu=native.
Add LLVM_CPUINFO environment variable to test mock /proc/cpuinfo
files for -mcpu=native

Co-authored-by: Elvina Yakubova <eyakubova@nvidia.com>
2024-10-29 13:34:43 +00:00
Freddy Ye
c4248fa3ed
[X86] Support MOVRS and AVX10.2 instructions. (#113274)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-25 09:00:19 +08:00
Freddy Ye
9e3d4653af
[X86] Update Model value for Arrow Lake. (#113273)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-23 09:44:26 +08:00
Albert Huang
aa2c0f35a1
[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU (#110085)
STAR-MC1 is an Armv8m CPU.

Technical specifications available at:

https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160
2024-10-14 15:48:12 +01:00
RipleyTom
c5f7a32356
[X86] Add AMD Llano family detection (#111312)
Very simple one liner, adds the missing detection for the Llano family
which is essentially a refreshed K10:
Documentation of the family id:
https://en.wikichip.org/wiki/amd/cpuid#Family_18_.2812h.29
Documentation that it fits into amdfam10:
https://en.wikipedia.org/wiki/AMD_10h#12h
2024-10-07 08:33:26 -07:00
Yingwei Zheng
bf895c714e
[RISCV] Bump hwprobe support to Linux 6.11 (#108578)
This patch is the follow-up of
https://github.com/llvm/llvm-project/pull/94352 with some updates:
1. Add support for more extensions for `zve*`, `zimop`, `zc*`, `zcmop`
and `zawrs`.
2. Use `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF` to check whether the
processor supports fast misaligned scalar memory access.
https://github.com/llvm/llvm-project/pull/108551 reminds me that the
patch
https://lore.kernel.org/all/20240809214444.3257596-1-evan@rivosinc.com/T/
has been merged. Address comment
https://github.com/llvm/llvm-project/pull/94352#discussion_r1626056015.

References:
1. constants:
https://github.com/torvalds/linux/blame/v6.11-rc7/arch/riscv/include/uapi/asm/hwprobe.h
2. https://docs.kernel.org/arch/riscv/hwprobe.html
3. Related commits:
1. `zve*` support:
de8f8282a9
2. `zimop` support:
36f8960de8
3. `zc*` support:
0ad70db5eb
4. `zcmop` support:
fc078ea317
5. `zawrs` support:
244c18fbf6
6. scalar misaligned perf:
c42e2f0767
and
1f5288874d
2024-10-05 11:00:09 +08:00
Jubilee
b8028f6b87
[TargetParser][AArch64] Believe runtime feature detection (#95694)
In https://github.com/llvm/llvm-project/issues/90365 it was reported
that TargetParser arrives at the wrong conclusion regarding what
features are enabled when attempting to detect "native" features on the
Raspberry Pi 4, because it (correctly) detects it as a Cortex-A72, but
LLVM (incorrectly) believes all Cortex-A72s have crypto enabled. Attempt
to help ourselves by allowing runtime information derived from the host
to contradict whatever we believe is "true" about the architecture.
2024-10-02 08:28:57 +01:00
Alex Bradbury
614aeda93b
[RISCV] Mark Zacas as non-experimental (#109651)
The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. The
ABI issue has been resolved by #101023 so I believe there's no known
barrier to moving Zacas to non-experimental.
2024-09-25 06:14:43 +01:00
Ganesh
02e4186d0b
[X86] AMD Zen 5 Initial enablement (#107964)
This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
2024-09-13 17:45:33 +01:00
Phoebe Wang
259ca9ee9c
Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (#101616)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-03 09:26:07 +08:00
Phoebe Wang
2e0588d5e1
Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions" (#101612)
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.
2024-08-02 13:04:10 +08:00
Phoebe Wang
10bad2c8d7
[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-08-02 12:10:50 +08:00
Shengchen Kan
95e9afff30 [X86] Update sub-features of APX for host CPU
This is a follow-up for https://github.com/llvm/llvm-project/pull/80636
2024-07-30 18:09:58 +08:00
Aiden Grossman
599f8e1120 Reland "[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)"
This reverts commit f1905f064451bf688577976a13000c9c47e58452.

This relands commit 19cf8deabe1124831164987f1b9bf2f806c0a875.

There were issues with the preprocessor includes that should have
excluded MSVC still including clang functions building on windows and
using intrin.h. This relanding fixes this behavior by additionally
wrapping the uses of __get_cpuid and __get_cpuid_count in _MSC_VER so
that clang in MSVC mode, which includes intrin.h, does not have any
conflicts.
2024-07-24 03:58:23 +00:00
azhan92
1df4d866cc
[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)
This PR adds support for -mcpu=pwr11/power11 and -mtune=pwr11/power11 in
clang and llvm.
2024-07-23 09:49:41 -04:00
Ami-zhang
fcec298087
[LoongArch] Support la664 (#100068)
A new ProcessorModel called `la664` is defined in LoongArch.td to
support `-march/-mtune=la664`.
2024-07-23 15:14:20 +08:00
Alex Bradbury
70e7d26e56
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
As discussed at the last sync-up call, mark Zacas as experimental until
this ABI issue is resolved
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>.

Don't return Zacas in getHostCPUFeatures (leaving a TODO there) as even if requesting detection of "native" features, the user likely doesn't want to automatically opt in to experimental codegen.
2024-07-23 08:06:15 +01:00
Yingwei Zheng
578cf724de
[RISCV] Add support for getHostCPUFeatures using hwprobe (#94352)
This patch adds support for `sys::getHostCPUFeatures` using the RISC-V
hardware probing interface.
References:
+ Loongarch patch:
e53f41c39f
+ asm/hwprobe.h:
2ab7951410/arch/riscv/include/uapi/asm/hwprobe.h
+ glibc support:
https://inbox.sourceware.org/glibc-cvs/20240301151728.AD5963858C53@sourceware.org/T/#Z2e.:..:20240301151728.AD5963858C53::40sourceware.org:1sysdeps:unix:sysv:linux:riscv:sys:hwprobe.h
+ __NR_riscv_hwprobe syscall tutorial:
https://github.com/cyyself/hwprobe
+ hwprobe docs: https://docs.kernel.org/arch/riscv/hwprobe.html

---------

Co-authored-by: Yangyu Chen <cyy@cyyself.name>
2024-07-16 10:11:39 +08:00
David Spickett
18e70a4d50
[llvm][TargetParser] Return StringMap from getHostCPUFeatures (#97824)
Previously this took a reference to a map and returned a bool to say
whether it succeeded. We can return a StringMap instead, as all callers
but 1 simply iterated the map if the bool was true, and passed in empty
maps as the starting point.

lldb's lit-cpuid did specifically check whether the call failed, but due
to the way the x86 routines work this works out the same as checking if
the returned map is empty.
2024-07-11 10:32:43 +01:00
Aiden Grossman
f1905f0644 Revert "[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)"
This reverts commit f6616e99c71c15d530060346ec29c3246d7fc235.

Was causing buildbot failures on Windows. I also remember seeing a
AMDGPU buildbot failing somewhere on a warning as they have -Werror
enabled.
2024-07-09 01:14:02 +00:00
Aiden Grossman
f6616e99c7 Reland "Revert "[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)""
This reverts commit 2039e130649d8469bc85fa31ba7422d1d3739f90.

This relands commit 19cf8deabe1124831164987f1b9bf2f806c0a875.

Added some additional preprocessor directives to ensure that Host.cpp
only includes cpuid.h when being built on x86.
2024-07-08 21:47:40 +00:00
Haojian Wu
3f9bff3df2 Remove an extra tokens at end of #undef directive, NFC 2024-07-08 20:36:15 +02:00
Aiden Grossman
87e914db85
[compiler-rt][X86] Unify getAMDProcessorTypeAndSubType (#97863)
This patch unifies the implementation of getAMDProcessorTypeAndSubtype
between compiler-rt and LLVM.

This patch is intended to be a step towards pulling these functions out
into identical .inc files to better facilitate code sharing between LLVM
and compiler-rt.
2024-07-08 11:03:29 -07:00
Aiden Grossman
2039e13064 Revert "[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)"
This reverts commit 19cf8deabe1124831164987f1b9bf2f806c0a875.

This was causing quite a few buildbot failures (see the PR description).
Reverting for now while I have time to sort it out. Seems like it should
just be conditional preprocessor macros for X86 however.
2024-07-08 18:00:51 +00:00
Aiden Grossman
19cf8deabe
[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)
This patch makes the host/feature detection in compiler-rt and LLVM use
the functions provided in cpuid.h(__get_cpuid, __get_cpuid_count)
instead of inline assembly. This simplifies the implementation and moves
any inline assembly away to a more common place.

A while ago, some similar cleanup was attempted, but this ended up
resulting in some compilation errors due to toolchain minimum version
issues (https://bugs.llvm.org/show_bug.cgi?id=30384). After the
reversion landed, there have been no attempts since then to clean up the
code, even though the minimum supported compilers now support the
relevant functions (https://godbolt.org/z/o1Mjz8ndv).
2024-07-08 10:54:35 -07:00
Jonathan Thackray
e80c59556d
[AArch64] Add support for Cortex-A725 and Cortex-X925 (#95214)
Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest
2024-06-13 00:00:57 +01:00
Jonathan Thackray
917afa8832
[ARM] Add support for Cortex-R52+ (#94633)
Cortex-R52+ is an Armv8-R AArch32 CPU.

Technical Reference Manual for Cortex-R52+:
   https://developer.arm.com/documentation/102199/latest/
2024-06-07 11:03:32 +01:00
Wei Zhao
6b9753a0ec
[AArch64] Add support for Qualcomm Oryon processor (#91022)
Oryon is an ARM V8 AArch64 CPU from Qualcomm.

---------

Co-authored-by: Wei Zhao <wezhao@qti.qualcomm.com>
2024-06-06 07:27:50 -07:00
Freddy Ye
4def1ce101
Reland "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93136)
This reverts commit aa4069ea96e5eb62bc8c7895b9d920f129611b3a.
2024-05-24 13:46:34 +08:00
Freddy Ye
aa4069ea96
Revert "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93123)
This reverts commit 282d2ab58f56c89510f810a43d4569824a90c538.
2024-05-23 10:25:23 +08:00
Freddy Ye
282d2ab58f
[X86] Remove knl/knm specific ISAs supports (#92883)
Cont. patch after https://github.com/llvm/llvm-project/pull/75580
2024-05-23 09:46:44 +08:00
Phoebe Wang
87f3407856
[X86][Driver] Do not add -evex512 for -march=native when the target doesn't support AVX512 (#91694) 2024-05-10 13:25:37 +08:00
Jonathan Thackray
e50a857fb1
[AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (#90440) 2024-04-30 14:15:01 +01:00
Phoebe Wang
b3291793f1
[X86] Enable EVEX512 when host CPU has AVX512 (#90479)
This is used when -march=native run on an unknown CPU to old version of
LLVM.
2024-04-30 10:09:41 +08:00
Jonathan Thackray
a670cdadca
[AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143)
Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
   https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
   https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
   https://developer.arm.com/documentation/101595/latest/
2024-04-26 13:04:35 +01:00
Jonathan Thackray
e85bfa6565
[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (#85401)
[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs

Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520AE:
   https://developer.arm.com/documentation/107726/latest/

Technical Reference Manual for Cortex-A720AE:
   https://developer.arm.com/documentation/102828/latest/
2024-03-19 10:04:51 +00:00
Jonathan Thackray
99be3875fb
[ARM][AArch64] Add missing Arm CPU part-ids to enable -mcpu=native (#84899)
Update Host.cpp with some missing Arm CPU part identifiers,
to enable `-mcpu=native` on these processors. These are found in
the Technical Reference Manuals listed under "part num" or "part no"
2024-03-13 11:19:32 +00:00