4 Commits

Author	SHA1	Message	Date
Craig Topper	29463612d2	[RISCV] Replace RISCV -> RISC-V in comments. NFC ... To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. More patches will follow. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146449	2023-03-27 09:50:17 -07:00
Craig Topper	ece4bb5ab8	[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. ... This information is not preserved in MIR today. So this patch adds information to RISCVMachineFunctionInfo when the vreg is created for the argument. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D134621	2022-10-04 15:39:10 -07:00
Matt Arsenault	cc5a1b3dd9	llvm-reduce: Add cloning of target MachineFunctionInfo ... MIR support is totally unusable for AMDGPU without this, since the set of reserved registers is set from fields here. Add a clone method to MachineFunctionInfo. This is a subtle variant of the copy constructor that is required if there are any MIR constructs that use pointers. Specifically, at minimum fields that reference MachineBasicBlocks or the MachineFunction need to be adjusted to the values in the new function.	2022-06-07 10:14:48 -04:00
Kito Cheng	690085c9b7	[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file ... RISCVMachineFunctionInfo has some fields like VarArgsFrameIndex and VarArgsSaveSize are calculated at ISel lowering stage, those info are not contained in MIR files, that cause test cases rely on those field can't not reproduce correctly by MIR dump files. This patch adding the MIR read/write for those fields. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D123178	2022-04-08 11:55:48 +08:00