4 Commits

Author	SHA1	Message	Date
Craig Topper	0f4c9c016c	[RISCV] Replace RISCV->RISC-V in strings. ... To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. D146449 already updated comments. Strings may have more user impact. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146451	2023-03-27 09:50:17 -07:00
Piyou Chen	3b8c0b342e	[RISCV] Add new pass to transform undef to pseudo for vector values. ... RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735	2023-02-22 04:03:22 -08:00
Fangrui Song	6f3e6a765a	Revert D129735 "[RISCV] Add new pass to transform undef to pseudo for vector values." ... This reverts commit f1c4241fb6e50c507adafbe14faf82a755ab92ca. It causes use-after-poison asan failures for CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll and CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll	2023-02-15 11:51:08 -08:00
Piyou Chen	f1c4241fb6	[RISCV] Add new pass to transform undef to pseudo for vector values. ... RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735	2023-02-14 19:42:44 -08:00