13 Commits

Author SHA1 Message Date
Craig Topper
09f6bdda24 [RISCV] Remove INVALID from the list of CPUs in RISCVTargetParser. NFC
This value is never used outside and is only used as a sentinel
internally which we can solve with other means.
2023-05-01 15:26:09 -07:00
Craig Topper
29463612d2 [RISCV] Replace RISCV -> RISC-V in comments. NFC
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449
2023-03-27 09:50:17 -07:00
NAKAMURA Takumi
9c93e728bf llvm-tblgen: Rewrite emitters to use TableGen::Emitter
Each emitter became self-contained since it has the registration of option.

Differential Revision: https://reviews.llvm.org/D144351
2023-03-21 16:21:27 +09:00
Craig Topper
e9c5d8007e [RISCV] Use 'unsigned' for XLen in RISCVTargetDefEmitter.cpp. NFC
The values are small so the difference doesn't matter, but the
consuming function is defined to take 'unsigned'.
2023-03-18 01:00:48 -07:00
Craig Topper
d80b7fde92 Recommit "[RISCV][TableGen] Move XLen detection into getMArch in RISCVTargetDefEmitter. NFC"
Using the correct feature name to detect 64bit this time. Previously,
I mistakenly compared the expected record name against a string inside
the record.
2023-01-20 12:20:58 -08:00
Craig Topper
8d25c73e39 Revert "[RISCV][TableGen] Move XLen detection into getMArch in RISCVTargetDefEmitter. NFC"
This reverts commit e58010f712ccac83194852fa95ed70ef76ba6a33.

Seems this is failing on the build bots.
2023-01-20 10:45:13 -08:00
Craig Topper
e58010f712 [RISCV][TableGen] Move XLen detection into getMArch in RISCVTargetDefEmitter. NFC
We no longer need the XLen in two places. Fold it into the code
that determines the default march.
2023-01-20 10:16:28 -08:00
Craig Topper
0ccbf91166 [RISCV] Remove Features from CPUInfo in RISCVTargetParser.
Instead of having separate feature bits, get information from march.
Invalid is now implied by empty march.
64-bit is now implied by march starting with "rv64".

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D142230
2023-01-20 10:03:37 -08:00
Craig Topper
e62ffd3fd6 [RISCV][TableGen] Use getAllDerivedDefinitions in RISCVTargetDefEmitter to simplify the code. NFC 2023-01-20 00:34:05 -08:00
wangpc
4954c3c7b6 [RISCV] Generate march string from target features
As what has been mentioned in D137517, this patch is to simplify
processors definitions in RISCV.td. We don't have to specify march
string since we can generate it from target features.

Reviewed By: fpetrogalli, kito-cheng

Differential Revision: https://reviews.llvm.org/D141479
2023-01-16 12:03:59 +08:00
Francesco Petrogalli
ac1ffd3cac [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.
Rework the change to prevent build failures. NFCI.

The failing code was submitted as
cf7a8305a2b4ddfd299c748136cb9a2960ef7089 and reverted via
8bd65e535fb33bc48805bafed8217b16a853e158.

The rework in this new commit prevents failures like the following:

FAILED: tools/clang/lib/Basic/CMakeFiles/obj.clangBasic.dir/Targets/RISCV.cpp.o
/usr/bin/c++  [bunch of non interesting stuff]  -c <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
In file included from <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp:19:
<path-to>/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:29:10: fatal error: llvm/TargetParser/RISCVTargetParserDef.inc: No such file or directory
  29 | #include "llvm/TargetParser/RISCVTargetParserDef.inc"
     |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

These failures happen because the library LLVMTargetParser depends on
RISCVTargetParserTableGen, which is a tablegen target that generates
the list of CPUs in
llvm/TargetParser/RISCVTargetParserDef.inc. This *.inc file is
included by the public header file
llvm/TargetParser/RISCVTargetParser.h.

The header file llvm/TargetParser/RISCVTargetParser.h is also used in
components (clangDriver and clangBasic) that link into
LLVMTargetParser, but on some configurations such components might end
up being built before TargetParser is ready.

The fix is to make sure that clangDriver and clangBasic depend on the
tablegen target RISCVTargetParserTableGen, which generates the .inc
file whether or not LLVMTargetParser is ready.

WRT the original patch at https://reviews.llvm.org/D137517, this
commit is just adding RISCVTargetParserTableGen in the DEPENDS list of
clangDriver and clangBasic.
2023-01-11 11:18:44 +01:00
Francesco Petrogalli
8bd65e535f Revert "[TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen."
This reverts commit cf7a8305a2b4ddfd299c748136cb9a2960ef7089.
2023-01-11 10:22:56 +01:00
Francesco Petrogalli
cf7a8305a2 [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.
This patch removes the file `llvm/include/llvm/TargetParser/RISCVTargetParser.def` and replaces it with a tablegen-generated `.inc` file out of `llvm/lib/Target/RISCV/RISCV.td`.

The module system has been updated to make sure we can build clang/llvm with `-DLLVM_ENABLE_MODULES=On`

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137517
2023-01-11 10:00:04 +01:00