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4 Commits

Author SHA1 Message Date
Simon Pilgrim
d391e4fe84 [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth.

Helps prevent future scheduler model mismatches like those that were only addressed in D44687.

Differential Revision: https://reviews.llvm.org/D113302
 2021-11-07 15:06:54 +00:00
Scott Constable
ad4313fc83 [X86] Fix bug in -mlvi-cfi that may clobber a live register 
Fix for this bug: https://bugs.llvm.org/show_bug.cgi?id=47740

The fix uses the existing findDeadCallerSavedReg() function instead of a hacky heuristic to find a scratch register to clobber.

Differential Revision: https://reviews.llvm.org/D88925
 2020-10-07 18:33:51 -07:00
Scott Constable
0505181006 [X86] Fix to X86LoadValueInjectionRetHardeningPass for possible segfault 
`MBB.back()` could segfault if `MBB.empty()`. Fixed by checking for `MBB.empty()` in the loop.

Differential Revision: https://reviews.llvm.org/D77584
 2020-04-10 18:28:08 -07:00
Scott Constable
f95a67d8b8 [X86] Add RET-hardening Support to mitigate Load Value Injection (LVI) 
Adding a pass that replaces every ret instruction with the sequence:

pop <scratch-reg>
lfence
jmp *<scratch-reg>

where <scratch-reg> is some available scratch register, according to the
calling convention of the function being mitigated.

Differential Revision: https://reviews.llvm.org/D75935
 2020-04-03 12:08:34 -07:00