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9 Commits

Author SHA1 Message Date
Nikita Popov
1061511008 [X86PreAMXConfig] Use IRBuilder to insert instructions (NFC) 
Use an IRBuilder to insert instructions in preWriteTileCfg().
While here, also remove some unnecessary bool return values.

There are some test changes because the IRBuilder folds
"trunc i16 8 to i8" to "i8 8", and that has knock-on effects on
instruction naming.

I ran into this when converting tests to opaque pointers and
noticed that this pass introduces unnecessary "bitcast ptr to ptr"
instructions.
 2022-06-22 17:28:48 +02:00
Nikita Popov
fbb72530fe [X86PreAMXConfig] Use MapVector to fix non-determinism 
We generate code by iterating over this map, so make sure that the
order is deterministic.
 2022-06-22 16:57:33 +02:00
Bing1 Yu
56d5c46b49 [X86] Support __tile_stream_loadd intrinsic for new AMX interface 
Adding support for __tile_stream_loadd intrinsic.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D103784
 2021-06-11 17:28:43 +08:00
Xiang1 Zhang
d4bdeca576 [X86] Support AMX fast register allocation 
Differential Revision: https://reviews.llvm.org/D100026
 2021-05-08 14:21:11 +08:00
Xiang1 Zhang
bebafe01a7 Revert "[X86] Support AMX fast register allocation" 
This reverts commit 77e2e5e07d01fe0b83c39d0c527c0d3d2e659146.
 2021-05-08 13:43:32 +08:00
Xiang1 Zhang
77e2e5e07d [X86] Support AMX fast register allocation 2021-05-08 13:27:21 +08:00
Benjamin Kramer
df323ba445 Revert "[X86] Support AMX fast register allocation" 
This reverts commit 3b8ec86fd576b9808dc63da620d9a4f7bbe04372.

Revert "[X86] Refine AMX fast register allocation"

This reverts commit c3f95e9197643b699b891ca416ce7d72cf89f5fc.

This pass breaks using LLVM in a multi-threaded environment by
introducing global state.
 2021-04-29 18:56:33 +02:00
Xiang1 Zhang
c3f95e9197 [X86] Refine AMX fast register allocation 2021-04-25 14:20:53 +08:00
Xiang1 Zhang
3b8ec86fd5 [X86] Support AMX fast register allocation 
Differential Revision: https://reviews.llvm.org/D100026
 2021-04-25 09:45:41 +08:00