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315 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky
bf96703fb3 [AMDGPU][MC][GFX8+] Correct v_cndmask modifiers 
Correct v_cndmask_b32 to support abs/neg modifiers in dpp/sdwa/e64 variants.
Correct v_cndmask_b16 for proper disassembly of abs/neg modifiers in e64_dpp variants.

Differential Revision: https://reviews.llvm.org/D135900
 2022-10-14 19:37:27 +03:00
Dmitry Preobrazhensky
4e62d02db9 [AMDGPU][MC] Correct image_gather4h 
Correct encoding of image_gather4h for GFX9; disable this instruction for SI, CI and VI.

Differential Revision: https://reviews.llvm.org/D135605
 2022-10-11 14:41:27 +03:00
Dmitry Preobrazhensky
8f8e4e3b38 [AMDGPU][MC][GFX11] Correct v_fmac_.*_e64_dpp 
Differential Revision: https://reviews.llvm.org/D134961
 2022-10-07 16:21:55 +03:00
Joe Nash
203d0b0ee1 [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type. 
For V_CMP_CLASS_F16_t16_e64 and V_CMPX_CLASS_F16_t16_e64,
https://reviews.llvm.org/D133723 changed the value type of src1 from i32 to i16.
These src1 operands are 16 bits, therefore need to be encoded as true16
operands. So the _e32 type was correctly set to VGPR_32_Lo128.
In _e64 form the operand class went from
VSrc_b32 to VSrc_b16. For some reason, we cannot encode inline literals for
VSrc_b16, see 5f5f566b265db00f577ead268400d99f34ba9cdd. In this phase of
the true16 implementation, VSrc_b16 and VSrc_b32 are still similar,
except from that quirk of inlines. So set the operand class to regain
that function.

Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D134897
 2022-10-05 11:15:40 -04:00
Dmitry Preobrazhensky
f4b1cfa1cb [AMDGPU][MC][GFX11] Correct e64_dpp variants of v_movreld and v_movrelsd 
Differential Revision: https://reviews.llvm.org/D135079
 2022-10-05 16:47:18 +03:00
Dmitry Preobrazhensky
485c539391 [AMDGPU][MC][GFX11] Disable non-null src0 for s_waitcnt_*cnt 
Differential Revision: https://reviews.llvm.org/D134809
 2022-09-29 19:56:03 +03:00
Jay Foad
3822a01e0b [AMDGPU] Add GFX11 ds_bvh_stack_rtn_b32 instruction 
Differential Revision: https://reviews.llvm.org/D133928
 2022-09-15 16:46:14 +01:00
Dmitry Preobrazhensky
405b19bb67 [AMDGPU][MC][GFX11] Add disassembler tests for v_readfirstlane_b32 
Differential Revision: https://reviews.llvm.org/D133437
 2022-09-15 18:18:33 +03:00
Dmitry Preobrazhensky
b0eea8f440 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for MIMG instructions 
Differential Revision: https://reviews.llvm.org/D133411
 2022-09-15 18:04:34 +03:00
Dmitry Preobrazhensky
6d63a531e2 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPD instructions 
Differential Revision: https://reviews.llvm.org/D133414
 2022-09-09 13:10:55 +03:00
Dmitry Preobrazhensky
c07ea46f21 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3P instructions 
Differential Revision: https://reviews.llvm.org/D133412
 2022-09-09 13:06:44 +03:00
Dmitry Preobrazhensky
efa65ef281 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3 instructions 
Differential Revision: https://reviews.llvm.org/D133350
 2022-09-07 13:55:27 +03:00
Dmitry Preobrazhensky
a95b45d380 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP8 instructions 
Differential Revision: https://reviews.llvm.org/D133353
 2022-09-07 13:51:31 +03:00
Dmitry Preobrazhensky
c777c8f022 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP16 instructions 
Differential Revision: https://reviews.llvm.org/D133356
 2022-09-07 13:47:55 +03:00
Dmitry Preobrazhensky
67d148b63c [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPC and VOPC.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132737
 2022-08-26 21:38:55 +03:00
Dmitry Preobrazhensky
35e2107842 [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP2 and VOP2.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132733
 2022-08-26 21:32:55 +03:00
Dmitry Preobrazhensky
ad39f1fa8c [AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP1 and VOP1.DPP instructions 
Differential Revision: https://reviews.llvm.org/D132731
 2022-08-26 21:30:08 +03:00
Dmitry Preobrazhensky
8ff3cea076 [AMDGPU][MC][GFX11][NFC] Add missing tests for SOP instructions 
Differential Revision: https://reviews.llvm.org/D132404
 2022-08-24 13:45:20 +03:00
Dmitry Preobrazhensky
5e7d43ffef [AMDGPU][MC][GFX11][NFC] Update tests for FLAT instructions 
Differential Revision: https://reviews.llvm.org/D132402
 2022-08-24 13:38:09 +03:00
Dmitry Preobrazhensky
badf8aed30 [AMDGPU][MC][NFC] Rename disassembler tests 
Make test names more uniform.

Differential Revision: https://reviews.llvm.org/D132472
 2022-08-24 13:26:57 +03:00
Dmitry Preobrazhensky
8f3c160b8b [AMDGPU][MC][GFX8][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132469
 2022-08-24 13:13:22 +03:00
Dmitry Preobrazhensky
4b9016da0a [AMDGPU][MC][GFX9][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132409
 2022-08-23 13:13:36 +03:00
Dmitry Preobrazhensky
0a8dd8ef79 [AMDGPU][MC][GFX10][NFC] Consolidate tests by encoding 
Differential Revision: https://reviews.llvm.org/D132235
 2022-08-22 19:53:56 +03:00
Dmitry Preobrazhensky
e99f6df726 [AMDGPU][MC][GFX9][NFC] Split large test file 
Split gfx9_dasm_all.txt by instruction encoding.

Differential Revision: https://reviews.llvm.org/D132124
 2022-08-19 14:01:42 +03:00
Dmitry Preobrazhensky
bdb859c9a7 [AMDGPU][MC][GFX8][NFC] Split large test file 
Split gfx8_dasm_all.txt by instruction encoding.

Differential Revision: https://reviews.llvm.org/D132126
 2022-08-19 13:54:56 +03:00
Dmitry Preobrazhensky
7e29d5c04b [AMDGPU][MC][GFX10][NFC] Split large test 
Split gfx10_dasm_all.txt by encoding.

Differential Revision: https://reviews.llvm.org/D132044
 2022-08-18 12:39:34 +03:00
Dmitry Preobrazhensky
4e68834add [AMDGPU][MC][GFX11][NFC] Add tests for VOP1 and VOP2 16 bit opcodes 
Differential Revision: https://reviews.llvm.org/D131588
 2022-08-11 17:12:13 +03:00
Dmitry Preobrazhensky
eda6e49aa8 [AMDGPU][MC][GFX11][NFC] Correct tests for 16-bit VOP2 opcodes which use v128 or higher VGPRs 
Differential Revision: https://reviews.llvm.org/D131564
 2022-08-11 15:55:58 +03:00
Dmitry Preobrazhensky
9d1eeefbfe [AMDGPU][MC][GFX11][NFC] Rename tests 
Make test names more uniform.

Differential Revision: https://reviews.llvm.org/D131398
 2022-08-09 13:56:05 +03:00
Dmitry Preobrazhensky
fc4c1a86f3 [AMDGPU][MC][GFX11][NFC] Split large tests 
Differential Revision: https://reviews.llvm.org/D131397
 2022-08-09 13:24:23 +03:00
Dmitry Preobrazhensky
05b3aadfff [AMDGPU][MC][GFX11] Correct v_dot2_f16_f16 and v_dot2_bf16_bf16 
Enable SGPRs for the following operands of these opcodes:

- src operands of VOP3 variant.
- src2 operand of DPP variants.

Differential Revision: https://reviews.llvm.org/D130989
 2022-08-03 15:08:23 +03:00
Dmitry Preobrazhensky
ae553f9e49 [AMDGPU][MC][GFX10] Correct encoding of VOP3 v_cmpx* opcodes 
Encode dst=EXEC but allow disassembler accept any dst value.

Differential Revision: https://reviews.llvm.org/D130978
 2022-08-03 15:03:44 +03:00
Dmitry Preobrazhensky
bb901dcc5a [AMDGPU][MC][GFX940] Correct disassembly of MFMA opcodes 
Add a decoder table for GFX940 MFMA opcodes.

Differential Revision: https://reviews.llvm.org/D130759
 2022-08-01 16:00:47 +03:00
Petar Avramovic
e8d260753e [AMDGPU] gfx11 allow dlc for MUBUF atomics 
Add MC support for dlc in gfx11 MUBUF atomic instructions.

Differential Revision: https://reviews.llvm.org/D129075
 2022-08-01 12:18:01 +02:00
Mirko Brkusanin
6a1aa627fa [AMDGPU] Enable image_gather4h instruction for gfx10 and gfx11 
Differential Revision: https://reviews.llvm.org/D130764
 2022-07-29 15:42:06 +02:00
Dmitry Preobrazhensky
0eb9f18520 [AMDGPU][MC][GFX11] Correct encoding of VOP3/VOP3_DPP v_cmpx* opcodes 
Encode dst=EXEC but allow disassembler accept any dst value.

Differential Revision: https://reviews.llvm.org/D130345
 2022-07-26 17:36:22 +03:00
Petar Avramovic
8de1f04c77 [AMDGPU] gfx11 Fix VOP3 dot instructions 
Fix src modifiers for operands with bf16 type.
op_sel[0:1] are ignored.

Differential Revision: https://reviews.llvm.org/D129084
 2022-07-22 11:43:35 +02:00
Stanislav Mekhanoshin
523a99c0eb [AMDGPU] Support for gfx940 fp8 smfmac 
Differential Revision: https://reviews.llvm.org/D129908
 2022-07-18 12:12:41 -07:00
Stanislav Mekhanoshin
2695f0a688 [AMDGPU] Support for gfx940 fp8 mfma 
Differential Revision: https://reviews.llvm.org/D129906
 2022-07-18 11:49:56 -07:00
Stanislav Mekhanoshin
9fa5a6b7e8 [AMDGPU] Support for gfx940 fp8 conversions 
Differential Revision: https://reviews.llvm.org/D129902
 2022-07-18 11:48:43 -07:00
Dmitry Preobrazhensky
2a6532d542 [AMDGPU][MC][GFX11] Correct disassembly of *_e64_dpp opcodes which support op_sel 
These opcodes cannot be disassembled because op_sel operand is missing - it must be added manually.
See https://github.com/llvm/llvm-project/issues/56512 for detailed issue analysis.

Differential Revision: https://reviews.llvm.org/D129637
 2022-07-15 13:11:59 +03:00
Piotr Sobczak
4874838a63 [AMDGPU] gfx11 WMMA instruction support 
gfx11 introduces new WMMA (Wave Matrix Multiply-accumulate)
instructions.

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D128756
 2022-06-30 11:13:45 -04:00
Joe Nash
07b7fada73 [AMDGPU] gfx11 VOPD instructions MC support 
VOPD is a new encoding for dual-issue instructions for use in wave32.
This patch includes MC layer support only.

A VOPD instruction is constituted of an X component (for which there are
13 possible opcodes) and a Y component (for which there are the 13 X
opcodes plus 3 more). Most of the complexity in defining and parsing
a VOPD operation arises from the possible different total numbers of
operands and deferred parsing of certain operands depending on the
constituent X and Y opcodes.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D128218
 2022-06-24 11:08:39 -04:00
Dmitry Preobrazhensky
dcb24f93af [AMDGPU][MC][GFX11] Correct disassembly of VOP3.DPP8 opcodes 
Fix bug #56163.
Add W32/W64 tests for all VOP3.DPP opcodes.

Differential Revision: https://reviews.llvm.org/D128369
 2022-06-23 13:07:45 +03:00
Dmitry Preobrazhensky
485e8b4f63 [AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes 
Fix bugs https://github.com/llvm/llvm-project/issues/56091, https://github.com/llvm/llvm-project/issues/56065.

Differential Revision: https://reviews.llvm.org/D128075
 2022-06-20 14:23:07 +03:00
Dmitry Preobrazhensky
b26afab9d1 [AMDGPU][MC][GFX11] Correct src0 for dpp variants of v_cvt_*_e64 
Differential Revision: https://reviews.llvm.org/D127847
 2022-06-16 13:48:43 +03:00
Joe Nash
989bd57f98 [AMDGPU] gfx11 support add_f16 
The instruction was skipped in the earlier large patch adding
VOP2, https://reviews.llvm.org/D126917.

Reviewed By: rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D127697
 2022-06-14 08:59:45 -04:00
Dmitry Preobrazhensky
365d827f65 [AMDGPU][MC][GFX11] Correct ds_swizzle_b32 
Enable offset parsing.

Differential Revision: https://reviews.llvm.org/D127404
 2022-06-14 12:58:03 +03:00
Joe Nash
fd3304ef85 [AMDGPU] gfx11 EXECZ and VCCZ are no longer allowed to be used as 
sources to SALU and VALU instructions.

Contributors:
Baptiste Saleil <baptiste.saleil@amd.com>

Patch 20/N for upstreaming of AMDGPU gfx11 architecture

Depends on D126989

Reviewed By: rampitec, foad, #amdgpu

Differential Revision: https://reviews.llvm.org/D127143
 2022-06-10 10:03:43 -04:00
Ivan Kosarev
60d6fbb621 [AMDGPU][GFX9][GFX10] Support base+soffset+offset SMEM atomics. 
Resolves a part of
https://github.com/llvm/llvm-project/issues/38652

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D127314
 2022-06-10 13:22:41 +01:00