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5633 Commits

Author SHA1 Message Date
Chris Lattner
85ea83e821 Add some advice 
llvm-svn: 29324
 2006-07-27 04:24:14 +00:00
Jim Laskey
3b4866e194 Use the predicate. 
llvm-svn: 29322
 2006-07-27 02:05:13 +00:00
Nate Begeman
787565024a Support jump tables when in PIC relocation model 
llvm-svn: 29318
 2006-07-27 01:13:04 +00:00
Jim Laskey
c169b8798f Prevent creation of MachineDebugInfo for intel unless it is darwin. RC842. 
llvm-svn: 29317
 2006-07-27 01:12:23 +00:00
Evan Cheng
23a21c19d9 New entry. 
llvm-svn: 29310
 2006-07-26 21:49:52 +00:00
Chris Lattner
9e56e5c003 Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC. 
llvm-svn: 29307
 2006-07-26 21:12:04 +00:00
Evan Cheng
f6acb34d23 - Refactor the code that resolve basic block references to a TargetJITInfo 
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
  of code is emitted to flush the icache. This ensures correct execution
  on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.

llvm-svn: 29276
 2006-07-25 20:40:54 +00:00
Evan Cheng
66ed41cac1 Can't commute shufps. The high / low parts elements come from different vectors. 
llvm-svn: 29275
 2006-07-25 20:25:40 +00:00
Rafael Espindola
8902fd702b implement function calling of functions with up to 4 arguments 
llvm-svn: 29274
 2006-07-25 20:17:20 +00:00
Evan Cheng
c0577648c0 Done. 
llvm-svn: 29262
 2006-07-21 23:07:23 +00:00
Rafael Espindola
976c93a110 implemented sub 
correctly update the stack pointer in the prologue and epilogue

llvm-svn: 29244
 2006-07-21 12:26:16 +00:00
Evan Cheng
74065bedf2 This opt is now handled in DAG combine. 
llvm-svn: 29243
 2006-07-21 08:26:46 +00:00
Evan Cheng
4cf0238720 A splat of a vector constant of all zero or all one is the vector constant. 
llvm-svn: 29234
 2006-07-20 23:09:47 +00:00
Evan Cheng
f98bc5288e Missing a space. 
llvm-svn: 29233
 2006-07-20 22:52:28 +00:00
Evan Cheng
683b966485 Clean up. 
llvm-svn: 29228
 2006-07-20 21:37:39 +00:00
Evan Cheng
8a881f2309 New entry. 
llvm-svn: 29215
 2006-07-19 21:29:30 +00:00
Jim Laskey
181fb1c4d7 Do once flag never set to true. 
llvm-svn: 29214
 2006-07-19 19:33:08 +00:00
Jim Laskey
7c860afec6 Tidy up a few things. 
llvm-svn: 29213
 2006-07-19 19:32:06 +00:00
Jim Laskey
18debc21db Reduce size of routine. Shrinks .o by 37%. 
llvm-svn: 29210
 2006-07-19 17:53:32 +00:00
Chris Lattner
4f8eb5ccaf bswapped load/store instructions are only availble in indexed addressing form. 
As such, use xoaddr (indexed only), not xaddr for address selection.

This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.

llvm-svn: 29208
 2006-07-19 17:15:36 +00:00
Jim Laskey
5ba7c23cdd Bug#834 ICE (crash in code generator?) when building PCH . 
Missing Darwin check in Intel ATT ASM printer.

llvm-svn: 29204
 2006-07-19 11:54:50 +00:00
Evan Cheng
968a0b0309 Misc. new entry. 
llvm-svn: 29202
 2006-07-19 06:06:24 +00:00
Evan Cheng
02d8836cd5 INC / DEC instructions have shorter code size than ADD32ri8, etc. 
llvm-svn: 29194
 2006-07-19 00:27:29 +00:00
Evan Cheng
c767acd25a Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Rafael Espindola
bf3a17cd32 initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
llvm-svn: 29175
 2006-07-18 17:00:30 +00:00
Chris Lattner
b00b6c2e86 Make the implicit def instructions look like other instrs. 
llvm-svn: 29174
 2006-07-18 16:33:26 +00:00
Rafael Espindola
75269be065 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00
Chris Lattner
e1758d4cef Remove what little AIX support we have. It has never been tested and isn't 
complete.

llvm-svn: 29156
 2006-07-15 01:24:23 +00:00
Chris Lattner
2e1d01541a Add an out-of-line virtual method for X86DwarfWriter to give it a home. 
llvm-svn: 29153
 2006-07-14 23:05:05 +00:00
Chris Lattner
96aecb5d76 Add missing PPC64 extload/truncstores 
llvm-svn: 29140
 2006-07-14 04:42:02 +00:00
Chris Lattner
950dffaed6 Add a note 
llvm-svn: 29139
 2006-07-14 04:07:29 +00:00
Chris Lattner
077b86a078 Another fix in the rotate encodings, needed when the first two operands are not 
the same.

llvm-svn: 29136
 2006-07-13 21:52:41 +00:00
Chris Lattner
b42a945fd2 Print negative immediates as negative values instead of large constants 
when using the immshifted addressing mode.

llvm-svn: 29130
 2006-07-12 23:24:02 +00:00
Chris Lattner
dd57ac4871 Fix encoding of rotates, such as rldicl 
llvm-svn: 29128
 2006-07-12 22:08:13 +00:00
Chris Lattner
5b17dee741 Implement PPC64 relocations types 
llvm-svn: 29125
 2006-07-12 21:23:20 +00:00
Chris Lattner
1ec5e73b32 An overaggressive #ifdef allows a function to fall off the bottom of the 
function instead of returning a value.  This sometimes allowed the ppc32 jit
to be used in 64-bit mode.

llvm-svn: 29123
 2006-07-12 20:42:10 +00:00
Chris Lattner
c8db10725b Add information preventing several register class constraints from working. 
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll

llvm-svn: 29118
 2006-07-12 16:59:49 +00:00
Chris Lattner
6e662083d9 The PPC64 JIT needs register numbers to encode instructions. 
llvm-svn: 29114
 2006-07-11 20:53:55 +00:00
Evan Cheng
d5a086ab12 Emit inc / dec of registers as one byte instruction. 
llvm-svn: 29110
 2006-07-11 19:49:49 +00:00
Jim Laskey
f7300b2706 It was pointed out that DEBUG() is only available with -debug. 
llvm-svn: 29106
 2006-07-11 18:25:13 +00:00
Jim Laskey
c3d341ea98 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.

llvm-svn: 29105
 2006-07-11 17:58:07 +00:00
Rafael Espindola
185c5c2bdf add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
 2006-07-11 11:36:48 +00:00
Chris Lattner
298ef37e02 Implement the inline asm 'A' constraint. This implements PR825 and 
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll

llvm-svn: 29101
 2006-07-11 02:54:03 +00:00
Chris Lattner
71227c23b1 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. 
llvm-svn: 29096
 2006-07-11 00:48:23 +00:00
Evan Cheng
32860f42bb New entry. 
llvm-svn: 29091
 2006-07-10 21:42:16 +00:00
Evan Cheng
79cf9a5342 Fixed stack objects do not specify alignments, but their offsets are known. 
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.

llvm-svn: 29090
 2006-07-10 21:37:44 +00:00
Chris Lattner
a7976d329e Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps 
into i16/i32 load/stores.

llvm-svn: 29089
 2006-07-10 20:56:58 +00:00
Chris Lattner
9aabc1e16f Mark internal function static 
llvm-svn: 29085
 2006-07-10 19:53:12 +00:00
Rafael Espindola
e40a7e2aa2 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Evan Cheng
af5ae57333 Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail. 
llvm-svn: 29072
 2006-07-07 21:37:21 +00:00