8 Commits

Author SHA1 Message Date
Tim Gymnich
1d0005a69a
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
- rename `GISelKnownBits` to `GISelValueTracking` to analyze more than
just `KnownBits` in the future
2025-03-29 11:51:29 +01:00
Paul Bowen-Huggett
bbb53d1a8c
[NFC] Make AMDGPUCombinerHelper methods const (#121903)
(This replaces #121740. Sorry for wasting your time.)

This is a follow-up to a previous commit (ee7ca0d) which eliminated
several "TODO: make CombinerHelper methods const" remarks. As promised
in that ealier commit, this change completes the set by also making the
methods of AMDGPUCombinerHelper const so that the Helper member of
AMDGPUPreLegalizerCombinerImpl can be const rather than explicitly
mutable.
2025-01-10 22:43:14 +07:00
Vikash Gupta
fd6f8b3ce3
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
This combine pattern perform the below transformation.

fmul x, select(y, A, B)      -> fldexp (x, select i32 (y, a, b))
fmul x, select(y, -A, -B)   -> fldexp ((fneg x), select i32 (y, a, b))

where, A=2^a & B=2^b ; a and b are integers.

It is a follow-up PR to implement the above combine for globalIsel, as
the corresponding DAG combine has been done for SelectionDAG Isel
(#111109)
2025-01-06 17:42:38 +05:30
Rahul Joshi
1753008bbb
[NFC] Eliminate top-level "using namespace" from some headers. (#102751)
- Eliminate top-level "using namespace" from some headers.
2024-08-11 13:10:48 -07:00
Elliot Goodrich
972a4e889d [llvm] Fix include guards
Add missing include guards to LLVM header files that did not previously
have them and update existing include guards to ensure that they enclose
all non-whitespace, non-comment text to enable these headers for the
multiple-include optimization.

Differential Revision: https://reviews.llvm.org/D150511
2023-06-13 10:47:18 +01:00
Matt Arsenault
2f5a116cf7 AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8
If we have legal f16 instructions but no f16 med3, we can save
one instruction by expanding out the min/max sequence compared
to casting to f32 and casting back.
2023-05-23 08:48:25 +01:00
Matt Arsenault
ad041a8ce7 AMDGPU: Fix missing C++ mode comment 2023-05-18 19:44:56 +01:00
Mirko Brkusanin
db6bc2ab51 [AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
If possible fold fneg into instruction above if users cannot fold mods and we
know it will decrease instruction count.
Follows same logic as SDAG combiner in choosing opportunities to combine.

Differential Revision: https://reviews.llvm.org/D112827
2021-11-17 14:25:13 +01:00