Carl Ritson
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a3a3e6997b
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[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
- Algorithm operates over whole IR to attempt to minimize waits.
- Add support for VALU->VALU SGPR hazards via VA_SDST/VA_VCC.
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2025-01-30 11:21:11 +09:00 |
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Phoebe Wang
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1547382033
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[X86] Support lowering of FMINIMUMNUM/FMAXIMUMNUM (#121464)
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2025-01-06 21:28:58 +08:00 |
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Shilei Tian
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6548b6354d
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Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
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2024-11-08 20:21:16 -05:00 |
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Shilei Tian
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ca33649abe
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Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
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2024-11-08 16:36:35 -05:00 |
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Shilei Tian
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e215a1e27d
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[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)
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2024-11-08 13:05:35 -05:00 |
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Matt Arsenault
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5883ad34d6
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DAG: Handle vector legalization of minimumnum/maximumnum (#109779)
Follow the same patterns as the other min/max variants.
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2024-09-30 13:43:35 +04:00 |
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Matt Arsenault
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ee61a4db3c
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AMDGPU: Add tests for minimumnum/maximumnum intrinsics
Vector cases are broken, so leave those for later.
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2024-09-11 18:20:03 +04:00 |
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