Phoebe Wang
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ad704ff62b
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[X86][NF] Switch the order of Inst and &Target.getInstruction(NewRec) (#130739)
Because Inst is ordered by Instruction ID.
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2025-03-12 17:35:54 +08:00 |
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Kazu Hirata
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dbe812220c
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[TableGen] Avoid repeated hash lookups (NFC) (#126344)
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2025-02-08 00:48:30 -08:00 |
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Jay Foad
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4e8c9d2813
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[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)
Also use brace initialization and emplace to avoid explicitly
constructing std::pair, and the same for std::tuple.
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2025-01-16 13:20:41 +00:00 |
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Rahul Joshi
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62e2c7fb2d
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[LLVM][TableGen] Change all Init pointers to const (#112705)
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
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2024-10-18 07:50:22 -07:00 |
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Rahul Joshi
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32719c48ab
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[LLVM][TableGen] Change a few emitters to use const Record pointers (#110112)
Change DirectiveEmitter, Option Emitter, and X86 Emitters to use const
Record pointers.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
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2024-09-27 07:07:16 -07:00 |
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Rahul Joshi
|
1a793a8ca0
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[LLVM][TableGen] Change X86InstrMapping to use const RecordKeeper (#109066)
Change X86InstrMappingEmitter to use const RecordKeeper.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
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2024-09-18 10:41:21 -07:00 |
|
Rahul Joshi
|
bdf02249e7
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[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858)
Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to
const pointer.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
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2024-09-09 14:33:21 -07:00 |
|
Phoebe Wang
|
b0329206db
|
[X86][AVX10.2] Support AVX10.2 VNNI FP16/INT8/INT16 new instructions (#101783)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
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2024-08-05 18:57:42 +08:00 |
|
JaydeepChauhan14
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bddab518db
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[X86][MC,Driver] Support -msse2avx to encode SSE instruction with VEX prefix (#96860)
For GCC compatibility
https://gcc.gnu.org/onlinedocs/gcc-14.1.0/gcc/x86-Options.html.
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2024-07-16 09:40:45 +08:00 |
|
Shengchen Kan
|
bdc7840c57
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[X86][CodeGen] Share code between CompressEVEX pass and ND2NonND transform, NFCI
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2024-06-19 16:03:57 +08:00 |
|
Shengchen Kan
|
22c572eae0
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[X86][CodeGen] Support memory folding for NDD -> RMW
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2024-05-30 19:06:22 +08:00 |
|
Shengchen Kan
|
5988c798de
|
[X86][tablgen] Add assertions when emitting NF transform table
|
2024-05-28 21:09:36 +08:00 |
|
Shengchen Kan
|
17ecd23f69
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[X86][tablgen] Extend X86CompressEVEXTablesEmitter for NF transform
The generated table will be used in #93508
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2024-05-28 20:06:40 +08:00 |
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