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271 Commits

Author SHA1 Message Date
Chad Rosier
dccc4794e6 Use a temporary variable, rather then a series of redundant calls. 
llvm-svn: 150536
 2012-02-15 00:23:55 +00:00
Chad Rosier
5b9c3974d2 Remove unnecessary assignment to temporary, ResultReg. 
llvm-svn: 150520
 2012-02-14 22:29:48 +00:00
Chad Rosier
0ee8c513f7 [fast-isel] Add support for SUBs with non-legal types. 
llvm-svn: 150047
 2012-02-08 02:45:44 +00:00
Chad Rosier
bd471255a9 [fast-isel] Add support for ORs with non-legal types. 
llvm-svn: 150045
 2012-02-08 02:29:21 +00:00
Chad Rosier
ded4c99f2e [fast-isel] Add support for indirect branches. 
llvm-svn: 150014
 2012-02-07 23:56:08 +00:00
Craig Topper
e55c556a24 Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
Chad Rosier
685b20c114 [fast-isel] Add support for ADDs with non-legal types. 
llvm-svn: 149934
 2012-02-06 23:50:07 +00:00
Duncan Sands
ae22c60f90 Persuade GCC that there is nothing worth warning about here (there isn't). 
llvm-svn: 149834
 2012-02-05 14:20:11 +00:00
Chad Rosier
b84a4b4c64 [fast-isel] Add support for URem. 
llvm-svn: 149716
 2012-02-03 21:23:45 +00:00
Chad Rosier
e023d5d7f3 [fast-isel] Rename isZExt to isSigned. No functional change intended. 
llvm-svn: 149714
 2012-02-03 21:14:11 +00:00
Chad Rosier
aaa55a88b6 [fast-isel] Add support for UDIV. 
llvm-svn: 149712
 2012-02-03 21:07:27 +00:00
Chad Rosier
41f0e78b6c [fast-isel] Add support for FPToUI. Also add test cases for FPToSI. 
llvm-svn: 149706
 2012-02-03 20:27:51 +00:00
Chad Rosier
a8a8ac5d47 [fast-isel] Add support for selecting UIToFP. 
llvm-svn: 149704
 2012-02-03 19:42:52 +00:00
David Blaikie
46a9f016c5 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Eric Christopher
d284c1d80d Fix assert. 
llvm-svn: 147966
 2012-01-11 20:55:27 +00:00
Jakob Stoklund Olesen
083dbdca7f Match SelectionDAG logic for enabling movt. 
Darwin doesn't do static, and ELF targets only support static.

llvm-svn: 147740
 2012-01-07 20:49:15 +00:00
Jakob Stoklund Olesen
8cdce7e690 Use getRegForValue() to materialize the address of ARM globals. 
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.

<rdar://problem/10658692>

llvm-svn: 147720
 2012-01-07 04:07:22 +00:00
Jakob Stoklund Olesen
68f034ee1a Use movw+movt in ARMFastISel::ARMMaterializeGV. 
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.

This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.

<rdar://problem/10629774>

llvm-svn: 147712
 2012-01-07 01:47:05 +00:00
Evan Cheng
68132d8093 ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
llvm-svn: 146981
 2011-12-20 18:26:50 +00:00
Chad Rosier
ded6160473 VFP2 is required for FP loads. Noticed by inspection. 
llvm-svn: 146569
 2011-12-14 17:55:03 +00:00
Chad Rosier
fce28914ea Tidy up. 
llvm-svn: 146568
 2011-12-14 17:32:02 +00:00
Chad Rosier
a26979be29 Fix 80-column violation and extraneous brackets. 
llvm-svn: 146566
 2011-12-14 17:26:05 +00:00
Evan Cheng
7fae11b231 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function 
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
 2011-12-14 02:11:42 +00:00
Chad Rosier
563de603f7 [fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular 
load and then move the result from a GPR to a FPR.

llvm-svn: 146502
 2011-12-13 19:22:14 +00:00
Evan Cheng
7f8e563a69 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
 2011-12-07 07:15:52 +00:00
Chad Rosier
c77830d21e [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

llvm-svn: 145891
 2011-12-06 01:44:17 +00:00
Bob Wilson
80381f6cbf Fix 80-column issues. 
llvm-svn: 145783
 2011-12-04 00:52:23 +00:00
Chad Rosier
ec3b77e00d [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

llvm-svn: 145742
 2011-12-03 02:21:57 +00:00
Nick Lewycky
50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Chad Rosier
9fd0e55e91 [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Duncan Sands
12330650f8 Silence wrong warnings from GCC about variables possibly being used 
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.

llvm-svn: 145239
 2011-11-28 10:31:27 +00:00
Chad Rosier
ee93ff736a Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. 
llvm-svn: 144959
 2011-11-18 01:17:34 +00:00
Chad Rosier
0eff3e5c21 Add TODO comment. 
llvm-svn: 144920
 2011-11-17 21:46:13 +00:00
Chad Rosier
15b2498e88 Dead code. 
llvm-svn: 144888
 2011-11-17 07:24:49 +00:00
Chad Rosier
ce619ddfc5 Don't unconditionally set the kill flag. 
rdar://10456186

llvm-svn: 144872
 2011-11-17 01:16:53 +00:00
Chad Rosier
80979b6ea6 Check to make sure we can select the instruction before trying to put the 
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
 2011-11-16 18:39:44 +00:00
Chad Rosier
af13d767a2 Add FIXME comment. 
llvm-svn: 144743
 2011-11-16 00:32:20 +00:00
Jay Foad
0745e645e0 Remove some unnecessary includes of PseudoSourceValue.h. 
llvm-svn: 144631
 2011-11-15 07:24:32 +00:00
Chad Rosier
057b6d3476 Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
 2011-11-14 23:04:09 +00:00
Chad Rosier
ab7223e99a Add support for inlining small memcpys. 
rdar://10412592

llvm-svn: 144578
 2011-11-14 22:46:17 +00:00
Chad Rosier
45110fdf8d Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
 2011-11-14 22:34:48 +00:00
Chad Rosier
adfd200bcb Add support for Thumb load/stores with negative offsets. 
rdar://10412592

llvm-svn: 144565
 2011-11-14 20:22:27 +00:00
Chad Rosier
2a1df883d0 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592

llvm-svn: 144518
 2011-11-14 04:09:28 +00:00
Chad Rosier
1198d894d0 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
llvm-svn: 144494
 2011-11-13 09:44:21 +00:00
Chad Rosier
a476e391f1 Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier
5196efdf36 Fix comments. 
llvm-svn: 144490
 2011-11-13 04:25:02 +00:00
Chad Rosier
c8cfd3a8fb Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
 2011-11-13 02:23:59 +00:00
Chad Rosier
a7ebc5617d Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
llvm-svn: 144426
 2011-11-11 23:31:03 +00:00
Chad Rosier
e19b0a9eb8 Rename variables to avoid confusion. No functionallity change intended. 
llvm-svn: 144377
 2011-11-11 06:27:41 +00:00
Chad Rosier
7ddd63ce4e Add support for using immediates with select instructions. 
rdar://10412592

llvm-svn: 144376
 2011-11-11 06:20:39 +00:00