3 Commits

Author	SHA1	Message	Date
RolandF77	99f0309669	[PowerPC] catch v2i64 shift left by 1 is add case (#138772) ... Catch missing case in PPC BE for v2i64 x << 1 and generate x + x.	2025-05-13 11:26:46 -04:00
Nemanja Ivanovic	329b8cd3e3	[PowerPC] Improve code gen for vector add ... Improve codegen for vectors modulo additions. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D154447	2023-07-13 15:21:49 -04:00
Lei Huang	c7c3d71414	[PowerPC] add testcase for vector add and shift	2023-07-04 10:45:19 -04:00