In this commit:
(1) Added new pass manager support for `ReachingDefAnalysis`.
(2) Added printer pass.
(3) Make old pass manager use `ReachingDefInfoWrapperPass`
Demonstrates the failure to keep avx512 mask predicate bit manipulation
patterns (based off the BMI1/BMI2/TBM style patterns) on the predicate
registers - unless the pattern is particularly complex the cost of
transferring to/from gpr outweighs any gains from better scalar
instructions
I've been rather random with the mask types for the tests, I can adjust
later on if there are particular cases of interest
As reported in https://github.com/llvm/llvm-project/issues/141034
SelectionDAG::getNode had some unexpected
behaviors when trying to create vectors with UNDEF elements. Since
we treat both UNDEF and POISON as undefined (when using isUndef())
we can't just fold away INSERT_VECTOR_ELT/INSERT_SUBVECTOR based on
isUndef(), as that could make the resulting vector more poisonous.
Same kind of bug existed in DAGCombiner::visitINSERT_SUBVECTOR.
Here are some examples:
This fold was done even if vec[idx] was POISON:
INSERT_VECTOR_ELT vec, UNDEF, idx -> vec
This fold was done even if any of vec[idx..idx+size] was POISON:
INSERT_SUBVECTOR vec, UNDEF, idx -> vec
This fold was done even if the elements not extracted from vec could
be POISON:
sub = EXTRACT_SUBVECTOR vec, idx
INSERT_SUBVECTOR UNDEF, sub, idx -> vec
With this patch we avoid such folds unless we can prove that the
result isn't more poisonous when eliminating the insert.
Fixes https://github.com/llvm/llvm-project/issues/141034
With this change, construction of abstract subprogram DIEs is split in
two stages/functions:
creation of DIE (in DwarfCompileUnit::getOrCreateAbstractSubprogramDIE)
and its population with children (in
DwarfCompileUnit::constructAbstractSubprogramScopeDIE).
With that, abstract subprograms can be created/referenced from
DwarfDebug::beginModule, which should solve the issue with static local
variables DIE creation of inlined functons with optimized-out
definitions. It fixes https://github.com/llvm/llvm-project/issues/29985.
LexicalScopes class now stores mapping from DISubprograms to their
corresponding llvm::Function's. It is supposed to be built before
processing of each function (so, now LexicalScopes class has a method
for "module initialization" alongside the method for "function
initialization"). It is used by DwarfCompileUnit to determine whether a
DISubprogram needs an abstract DIE before DwarfDebug::beginFunction is
invoked.
DwarfCompileUnit::getOrCreateSubprogramDIE method is added, which can
create an abstract or a concrete DIE for a subprogram. It accepts
llvm::Function* argument to determine whether a concrete DIE must be
created.
This is a temporary fix for
https://github.com/llvm/llvm-project/issues/29985. Ideally, it will be
fixed by moving global variables and types emission to
DwarfDebug::endModule (https://reviews.llvm.org/D144007,
https://reviews.llvm.org/D144005).
Some code proposed by Ellis Hoag <ellis.sparky.hoag@gmail.com> in
https://github.com/llvm/llvm-project/pull/90523 was taken for this
commit.
The MCContext::getOrCreateSymbol change in #138817 was a workaround.
With #158106, we can replace `getOrCreateSymbol` with `parseSymbol`, in
llvm/lib/MC/MCParser to handle backslash-escaped symbols.
Fixes https://github.com/llvm/llvm-project/issues/158415.
After `resolveTargetShuffleInputsAndMask` and other modifications on
`Ops` and `Mask`, unused inputs in `Ops` are erased, and may leave `Ops`
empty. This patch handles such cases before calling the final
`combineX86ShuffleChain`。
Fix regression after 62f2641d603db9aef99dd5c434a1dfe7d3f56346. Previous
patch handled the register case, but the memory case snuck another use
of ptr_rc_tailcall hidden inside i64mem_TC
Apply the following changes:
* Ensure all float types are covered (`f16` and `f128` were often
missing)
* Switch to more straightforward test names
* Remove some CHECK directives that are outdated (prefix changed but the
directive did not get removed)
* Add common check prefixes to merge similar blocks
* Test a more similar set of platforms
* Add missing `nounwind`
* Test `strictfp` for each libcall where possible
This is a pre-test for [1].
[1]: https://github.com/llvm/llvm-project/pull/152684
Match `(X * Y) + Z` in `combineAdd`. If target supports and we don't
overflow (ie. we know the top 12 bits are unset), rewrite using
VPMADD52L
Have just done the `L` version for now at least, wanted to get feedback
before continuing
Checking `isOperationLegalOrCustom` instead of `isOperationLegal` allows
more optimization opportunities. In particular, if a target wants to
mark `extract_vector_elt` as `Custom` rather than `Legal` in order to
optimize some certain cases, this combiner would otherwise miss some
improvements.
Previously, using `isOperationLegalOrCustom` was avoided due to the risk
of getting stuck in infinite loops (as noted in
61ec738b60).
After testing, the issue no longer reproduces, but the coverage is
limited to the regression/unit tests and the test-suite.
Allows us to extend a result back to the largest type after we've handled mask logic using vXi1 result types from different source vector widths (e.g. v8i32 and v8i8)
Fixes#157382
As observed by @mikaelholmen, PR #130988
"[AMDGPU] Implement IR expansion for frem instruction" introduced a
regression on x86. Its changes led to the pass being skipped on
functions with the optnone attribute. @bjope also noted that a check
concerning the optnone handling is wrong.
This patch fixes both issues which together fixes the regression. During
the review it was observed that, even before PR #130988, the pass would
not run on optnone functions with the new pass manager. This is also
fixed.
The 256-bit maximum vector register size control was removed from AVX10
whitepaper, ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
We have warned these options in LLVM21 through #132542. This patch
removes underlying implementations in LLVM22.
This hook replaces inline asm with LLVM intrinsics. It was intended to
match inline assembly implementations of bswap in libc headers and
replace them more optimizable implementations.
At this point, it has outlived its usefulness (see
https://github.com/llvm/llvm-project/issues/156571#issuecomment-3247638412),
as libc implementations no longer use inline assembly for this purpose.
Additionally, it breaks the "black box" property of inline assembly,
which some languages like Rust would like to guarantee.
Fixes https://github.com/llvm/llvm-project/issues/156571.
The generated MIR fails machine verifier as stack pointer is being
modified without appropriate attributes in frameInfo. This PR fixes this
issue by adding adjustsStack=true attribute. Fixes the post commit
regression identified in #155673.
According AMX ABI, tile registers (including config) are volatile hence
requiring caller to save/restore config register. This is done in X86's
FastPreTileConfig pass. Currently the PLDTILECFGV instruction is emitted
immediately after the call which can be problematic if call returns a
value in say rax register and AMX tile is configured using the same
register. This PR addresses this issue by ensuring that PLDTILECFGV is
sinked closer to first instruction using a tile after the call.
This patch implements a correctly rounded expansion of the frem
instruction in LLVM IR. This is useful for target architectures for
which such an expansion is too involved to be implement in ISel
Lowering. The expansion is based on the code from the AMD device libs
and has been tested successfully against the OpenCL conformance tests on
amdgpu. The expansion is implemented in the preexisting "expand-fp"
pass. It replaces the expansion of "frem" in ISel for the amdgpu target;
it is enabled for targets which do not directly support "frem" and for
which no matching "fmod" LibCall is available.
---------
Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com>
By only checking type legality we didn't account for 128/256-bit ops
being run on non-AVX512VL targets, or vXi8/i16 ops being run on
non-AVX512BW targets
This check is cropping up in several places now and I intend to hoist it
out into a common helper, but this initial fix needs to be as clean as
possible to be back ported to 21.X
Fixes#156256
- Moved llvm.set.rounding testcases from llvm/test/CodeGen/X86/fpenv.ll to
llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll.
- Added GlobalIsel RUNs as precommit test and will add llvm.set.rounding
GISEL implementation PR after this merge.
We already handle the case if the mask is one, so I added the other case where the op is replaced with a MOVSH/S/D blend.
This assumes the scalar passthrough is op0.
I had to adjust the test case for #98306 as AFAICT it'd been over
reduced
Fixes#153570
* `SetFrame` does not count as a stack allocation.
* `mov` in the epilog undoes `SetFrame` (but is not required), it does
not deallocate a stack allocation.
* `mov` in the epilog MUST be before any stack deallocation or register
popping.
* Remove assert for having a prolog without any epilogs (this is
possible for `noreturn` functions, for instance).
* Improve the errors in `MC` to include the problematic function name.
The goal is to remove redundant TEST*ri instructions, especially with NF
feature. Other tests are side effects due to longer live range of
EFLAGS. https://godbolt.org/z/PbaTj1oa3
Reland with fix to buildbot failures.
The AVX512 setcc combine in X86ISelLowering was calling
`APInt::getLowBitsSet` with a mask width (`Len`) that could exceed the
bit width of the broadcasted scalar operand
(`BroadcastOpVT.getSizeInBits()`), leading to assertion failures.
This patch replaces `Len` with the number of defined (non-undef)
elements in the constant pool vector.
This ensures the generated mask is valid and avoids crashes when the
constant pool contains more elements than the scalar bit width can
represent.
Fixes#155762
The goal is to remove redundant TEST*ri instructions, especially with NF
feature. Other tests are side effects due to longer live range of
EFLAGS. https://godbolt.org/z/PbaTj1oa3
