2292 Commits

Author SHA1 Message Date
Reid Kleckner
cf8933d1b7 Only provide MS builtins when -fms-extensions is on
We already have builtins that are only available in GNU mode, so this
mirrors that.

Reviewers: rsmith

Differential Revision: http://llvm-reviews.chandlerc.com/D2128

llvm-svn: 194615
2013-11-13 22:47:22 +00:00
Chad Rosier
e714a962b5 [AArch64] Tests for legacy AArch32 NEON scalar shift by immediate instructions.
A number of non-overloaded intrinsics have been replaced by thier overloaded
counterparts.

llvm-svn: 194599
2013-11-13 20:05:44 +00:00
Weiming Zhao
87bb4920e9 add intrinsics: __builtin_arm_{dmb,dsb} for ARM
llvm-svn: 194513
2013-11-12 21:42:50 +00:00
Daniel Sanders
8b59af15ed [mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
  asm ("ldi.w %w0, 1", "=f"(result));

Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.

MSA registers (including control registers) are supported in clobber lists.

llvm-svn: 194476
2013-11-12 12:56:01 +00:00
Daniel Sanders
9626df1eb2 [mips] Added fpu register tests to tests/CodeGen/mips-clobber-reg.c
llvm-svn: 194474
2013-11-12 11:38:20 +00:00
Daniel Sanders
923af19f29 [mips] Small fixes to test/CodeGen/mips-clobber-reg.c
Fixed the following:
- Whitespace at end of most lines
- $11 test actually testing $10

llvm-svn: 194473
2013-11-12 11:15:48 +00:00
Robert Lytton
eaf6f36e6d XCore target requires preferred alignment.
The xcore llvm backend does not handle 8 byte alignment viz:
  "%BadAlignment = alloca i64, align 8"
So getPreferredTypeAlign() must never overalign.

llvm-svn: 194462
2013-11-12 10:09:34 +00:00
Akira Hatanaka
c4baedd71d [mips] Partially revert r193640. Stack alignment should not be determined by
the floating point register mode.

llvm-svn: 194426
2013-11-11 22:10:46 +00:00
Chad Rosier
09f5251c4d [AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194407
2013-11-11 19:11:19 +00:00
Chad Rosier
249c714bb4 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
llvm-svn: 194395
2013-11-11 18:04:22 +00:00
Will Dietz
949ec546c4 ubsan: Only emit constants for filenames and type descriptors once.
Produces neater IR in significantly less time.

(~18% faster -O0 compile time for sqlite3 with -fsanitize=undefined)

llvm-svn: 194231
2013-11-08 01:09:22 +00:00
Jiangning Liu
c628af66c7 Implement AArch64 Neon instruction set Perm.
llvm-svn: 194124
2013-11-06 03:35:53 +00:00
Jiangning Liu
37f5bb1b28 Implement AArch64 Neon instruction set Bitwise Extract.
llvm-svn: 194119
2013-11-06 02:26:12 +00:00
Jiangning Liu
34a7109b47 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
llvm-svn: 194086
2013-11-05 17:42:24 +00:00
Kevin Qin
9eece7b5e0 Implemented aarch64 neon intrinsic vcopy_lane with float type.
llvm-svn: 194042
2013-11-05 02:05:44 +00:00
Justin Bogner
e0ccdb1a28 CodeGen: Test that simple expressions are simplified at -O0
llvm-svn: 193995
2013-11-04 16:13:23 +00:00
Bob Wilson
2c82c3d033 OS X 10.9+ and iOS 7+ support load/store of big atomic objects.
rdar://13973577

Patch by Fariborz Jahanian.

llvm-svn: 193935
2013-11-02 23:27:49 +00:00
Chad Rosier
74329d6cff [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
llvm-svn: 193817
2013-10-31 22:37:08 +00:00
Chad Rosier
bdca387884 [AArch64] Add support for NEON scalar shift immediate instructions.
llvm-svn: 193791
2013-10-31 19:29:05 +00:00
Daniel Sanders
d5f554f0bb [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
llvm-svn: 193695
2013-10-30 15:45:42 +00:00
Daniel Sanders
ab94b537d7 [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).

These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.

bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
  it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
  values is an uimm8, rather than when the condition is a uimm8 (which is
  covered by bmnzi.b)

compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
  is the same operation (see MSA.txt).

i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
  because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
  distinguishable from bmnzi.b.

vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).

llvm-svn: 193693
2013-10-30 15:20:38 +00:00
Chad Rosier
4d55e6e0a4 [AArch64] Add support for NEON scalar floating-point compare instructions.
llvm-svn: 193692
2013-10-30 15:20:07 +00:00
Daniel Sanders
d74b130cc9 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.

llvm-svn: 193687
2013-10-30 14:45:14 +00:00
Akira Hatanaka
618b29813a [mips] Align the stack to 16-bytes for -mfp64.
llvm-svn: 193640
2013-10-29 19:00:35 +00:00
Richard Smith
426a47bddb Fix a parser crash when there are #pragmas in a context which requires a single
statement (after a case label, if, etc). Patch by Olivier Goffart!

llvm-svn: 193545
2013-10-28 22:04:30 +00:00
Alp Toker
a933f94c92 FileCheckize
llvm-svn: 193474
2013-10-26 15:43:55 +00:00
Alp Toker
1774954274 Quote wildcard in test's grep argument
The * could otherwise cause shell pathname expansion.

llvm-svn: 193473
2013-10-26 14:52:48 +00:00
Manman Ren
c94122e05b Intrinsics: fix extract & insert when index is out of bound.
Now, all extract & insert intrinsics should have the correct and operation
to ignore higher bits.

rdar://15250497

llvm-svn: 193267
2013-10-23 20:33:14 +00:00
Daniel Sanders
ffd8df29b6 [mips][msa] Add intrinsics that map to pseudo-instructions.
Unlike the previously added intrinsics, these do not map to a single instruction
on MIPS32. They are provided for regularity (to round out the .[bhw] variants
of the same operation) and compatibility with GCC.

Includes:
  copy_[us].d, fill.d, insert.d, insve.d

llvm-svn: 193237
2013-10-23 10:12:44 +00:00
Richard Smith
6b53e224eb Split -fsanitize=bounds to -fsanitize=array-bounds (for the frontend-inserted
check using the ubsan runtime) and -fsanitize=local-bounds (for the middle-end
check which inserts traps).

Remove -fsanitize=local-bounds from -fsanitize=undefined. It does not produce
useful diagnostics and has false positives (PR17635), and is not a good
compromise position between UBSan's checks and ASan's checks.

Map -fbounds-checking to -fsanitize=local-bounds to restore Clang's historical
behavior for that flag.

llvm-svn: 193205
2013-10-22 22:51:04 +00:00
Rafael Espindola
d53ffa0a70 Treat aliases as definitions.
This fixes pr17639.

Before this patch clang would consider

void foo(void) __attribute((alias("__foo")));

a declaration. It now correctly handles it as a definition.

Initial patch by Alp Toker. I added support for variables.

llvm-svn: 193200
2013-10-22 21:39:03 +00:00
Manman Ren
be38b9e15f _mm_extract_epi16: use "& 7" when index is out of bound.
This is in line with implementation of _mm_extract_pi16.
rdar://15250497

llvm-svn: 193187
2013-10-22 19:24:42 +00:00
Chad Rosier
c2a0b13c25 [AArch64] Add the constraint to NEON scalar mla/mls instructions.
llvm-svn: 193118
2013-10-21 20:12:01 +00:00
Rafael Espindola
156f634aa1 Make this test pass -verify.
Instead of using not, just drop the fastcall attribute which was causing
an warning:

calling convention 'fastcall' ignored for this target

llvm-svn: 193110
2013-10-21 19:48:28 +00:00
Matheus Almeida
70fbf77546 [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
2013-10-21 11:47:56 +00:00
Chad Rosier
3c03dee1d1 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192971
2013-10-18 14:03:36 +00:00
Chad Rosier
e7465644c6 [AArch64] Add support for NEON scalar three register different instruction
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192909
2013-10-17 18:12:50 +00:00
Daniel Sanders
c835a9fe80 [mips][msa] Added most of the remaining builtins
Includes:
and.v, bmnz.v, bmz.v, bnz.[bhwdv], bz.[bhwdv], cfcmsa, ctcmsa, fcaf,
fcor, fcueq, fcul[et], fcun, fcune, fsaf, fsueq, fsul[et], fsun, fsune, ftrunc
hadd_[su].[hwd], hsub_[su].[hwd], insert.[bhw], insve.[bhw], ld.[bhwd],
move.v, nor.v, or.v, srar.[bhwd], srari.[bhwd], srlr.[bhwd], srlri.[bhwd],
st.[bhwd], subsus_u.[bhwd], subsuu_s.[bhwd], vshf.[bhwd], xor.v

llvm-svn: 192896
2013-10-17 13:57:25 +00:00
Chad Rosier
00eef17dbe [AArch64] Add support for NEON scalar negate instruction.
llvm-svn: 192845
2013-10-16 21:04:53 +00:00
Chad Rosier
e904137c01 [AArch64] Add support for NEON scalar absolute value instruction.
llvm-svn: 192844
2013-10-16 21:04:49 +00:00
Chad Rosier
069b90463d [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192801
2013-10-16 16:09:16 +00:00
Rafael Espindola
002667c32b On 32 bit windows, mangle stdcall and fastcall decls in clang.
This removes the dependency on the llvm mangler doing it for us. In isolation,
the benefit is that the testing of what mangling is applied is all in one place:
(C, C++) X (Itanium, Microsoft) are all handled by clang.

This also gives me hope that in the future the llvm mangler (and llvm-ar) will
not depend on TargetMachine.

llvm-svn: 192762
2013-10-16 01:40:34 +00:00
Chad Rosier
a70fb7b716 [AArch64] Add support for NEON scalar signed saturating absolute value and
scalar signed saturating negate instructions.

llvm-svn: 192734
2013-10-15 21:19:02 +00:00
Rafael Espindola
3efc492092 Also don't hardcode the order on this test.
llvm-svn: 192603
2013-10-14 16:18:39 +00:00
Rafael Espindola
e8d060dba9 Don't hardcode the order of the aliases.
llvm-svn: 192601
2013-10-14 16:05:12 +00:00
Chad Rosier
193573ec89 [AArch64] Add support for NEON scalar integer compare instructions.
llvm-svn: 192597
2013-10-14 14:37:40 +00:00
Manman Ren
f5d9d348f7 Turn struct-path aware TBAA on by default.
Use -no-struct-path-tbaa to turn it off.
This is the same as r191695, which was reverted because it depends on a
commit that has issues.

llvm-svn: 192497
2013-10-11 20:48:38 +00:00
Warren Hunt
8f8bad723d Adds Microsoft compatiable C++ record layout code to clang.
llvm-svn: 192494
2013-10-11 20:19:00 +00:00
Robert Lytton
2d1969584a XCore : Fix bug in XCoreABIInfo::EmitVAArg()
Incorrect handling of 'double' and 'long long int'

llvm-svn: 192436
2013-10-11 10:29:34 +00:00
Nick Lewycky
ce6a4aacb4 The emitted IR is the same, we need these flags to actually use the LLVM target.
Mark it as requiring the x86 target.

llvm-svn: 192417
2013-10-11 03:52:43 +00:00