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419 Commits

Author SHA1 Message Date
Matt Arsenault
5dfd466032 AMDGPU/GlobalISel: Fix G_ICMP for wave32 
llvm-svn: 366114
 2019-07-15 19:39:31 +00:00
Matt Arsenault
53fa759ff5 AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break 
llvm-svn: 366102
 2019-07-15 18:25:24 +00:00
Matt Arsenault
b390121efb AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf 
llvm-svn: 366099
 2019-07-15 18:18:46 +00:00
Matt Arsenault
a65913e752 AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR 
llvm-svn: 366087
 2019-07-15 17:26:43 +00:00
Matt Arsenault
e6d10f97dd AMDGPU/GlobalISel: Select G_SUB 
llvm-svn: 365484
 2019-07-09 14:05:11 +00:00
Matt Arsenault
872f38be7e AMDGPU/GlobalISel: Select G_UNMERGE_VALUES 
llvm-svn: 365483
 2019-07-09 14:02:26 +00:00
Matt Arsenault
9b7ffc4e55 AMDGPU/GlobalISel: Select G_MERGE_VALUES 
llvm-svn: 365482
 2019-07-09 14:02:20 +00:00
Matt Arsenault
50be3481d4 AMDGPU/GlobalISel: Try generated matcher with intrinsics 
llvm-svn: 364933
 2019-07-02 14:52:16 +00:00
Matt Arsenault
70a4d3f67c AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operands 
The register bank for the destination of the sample argument copy was
wrong. We shouldn't be constraining each source to the result register
bank. Allow constraining the original register to the right size.

llvm-svn: 364928
 2019-07-02 14:40:22 +00:00
Matt Arsenault
ed63399244 AMDGPU/GlobalISel: Select G_FENCE 
Manually select to workaround tablegen emitter emitting checks for
G_CONSTANT.

llvm-svn: 364927
 2019-07-02 14:17:38 +00:00
Matt Arsenault
9e8e8c60fa AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics 
llvm-svn: 364835
 2019-07-01 18:49:01 +00:00
Matt Arsenault
a310727830 AMDGPU/GlobalISel: Fail instead of assert when selecting loads 
llvm-svn: 364807
 2019-07-01 16:36:39 +00:00
Matt Arsenault
0a52e9d026 AMDGPU/GlobalISel: Complete implementation of G_GEP 
Also works around tablegen defect in selecting add with unused carry,
but if we have to manually select GEP, might as well handle add
manually.

llvm-svn: 364806
 2019-07-01 16:34:48 +00:00
Matt Arsenault
e1006259d8 AMDGPU/GlobalISel: Select G_PHI 
llvm-svn: 364805
 2019-07-01 16:32:47 +00:00
Tom Stellard
9e9dd30de3 AMDGPU/GlobalISel: Implement select for 32-bit G_ADD 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58804

llvm-svn: 364797
 2019-07-01 16:09:33 +00:00
Matt Arsenault
2ab25f9ceb AMDGPU/GlobalISel: Select G_BRCOND for vcc 
llvm-svn: 364795
 2019-07-01 16:06:02 +00:00
Matt Arsenault
cda82f0bb6 AMDGPU/GlobalISel: Select G_FRAME_INDEX 
llvm-svn: 364789
 2019-07-01 15:48:18 +00:00
Matt Arsenault
fdf36729c7 AMDGPU/GlobalISel: Make s16 select legal 
This is easy to handle and avoids legalization artifacts which are
likely to obscure combines.

llvm-svn: 364787
 2019-07-01 15:42:47 +00:00
Matt Arsenault
6464280eb0 AMDGPU/GlobalISel: Select G_BRCOND for scc conditions 
llvm-svn: 364786
 2019-07-01 15:39:27 +00:00
Matt Arsenault
1daad91af6 AMDGPU/GlobalISel: Tolerate copies with no type set 
isVCC has the same bug, but isn't used in a context where it can cause
a problem.

llvm-svn: 364784
 2019-07-01 15:23:04 +00:00
Matt Arsenault
4f64ade04c AMDGPU/GlobalISel: Select src modifiers 
llvm-svn: 364782
 2019-07-01 15:18:56 +00:00
Matt Arsenault
89fc8bcdd6 AMDGPU/GlobalISel: Fail on store to 32-bit address space 
llvm-svn: 364766
 2019-07-01 13:37:39 +00:00
Matt Arsenault
3b7668ae4b AMDGPU/GlobalISel: Improve icmp selection coverage. 
Select s64 eq/ne scalar icmp.

llvm-svn: 364765
 2019-07-01 13:34:26 +00:00
Matt Arsenault
9f992c238a AMDGPU/GlobalISel: Fix scc->vcc copy handling 
This was checking the size of the register with the value of the size,
which happens to be exec. Also fix assuming VCC is 64-bit to fix
wave32.

Also remove some untested handling for physical registers which is
skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical
copy source. I'm not sure if this should be trying to handle this
special case instead of dealing with this in copyPhysReg.

llvm-svn: 364761
 2019-07-01 13:22:07 +00:00
Matt Arsenault
5dafcb9b11 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate 
Zext from s1 is the only case where this should do anything with the
current legal extensions.

llvm-svn: 364760
 2019-07-01 13:22:06 +00:00
Matt Arsenault
d7ffa2a948 AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT 
llvm-svn: 364308
 2019-06-25 13:18:11 +00:00
Matt Arsenault
dbb6c03175 AMDGPU/GlobalISel: Select G_TRUNC 
llvm-svn: 364215
 2019-06-24 18:02:18 +00:00
Matt Arsenault
f8a841b88e AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1 
Try to fail for scc, since I don't think that should ever be produced.

llvm-svn: 364199
 2019-06-24 16:24:03 +00:00
Matt Arsenault
fee1949b35 AMDGPU/GlobalISel: Account for multiple defs when finding intrinsic ID 
llvm-svn: 363578
 2019-06-17 17:01:27 +00:00
Tom Stellard
8b1c53b528 AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT 
Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60640

llvm-svn: 363576
 2019-06-17 16:27:43 +00:00
Stanislav Mekhanoshin
a6322941ff [AMDGPU] gfx1010 VMEM and SMEM implementation 
Differential Revision: https://reviews.llvm.org/D61330

llvm-svn: 359621
 2019-04-30 22:08:23 +00:00
Tom Stellard
33634d1b25 AMDGPU/GlobalISel: Implement select for G_INSERT 
Re-commit r344310.

Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D53116

llvm-svn: 355159
 2019-03-01 00:50:26 +00:00
Tom Stellard
41f32196a0 AMDGPU/GlobalISel: Implement select for G_EXTRACT 
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D49714

llvm-svn: 355156
 2019-02-28 23:37:48 +00:00
Tom Stellard
79b5c3842b AMDGPU/GlobalISel: Move SMRD selection logic to TableGen 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D52922

llvm-svn: 354516
 2019-02-20 21:02:37 +00:00
Chandler Carruth
2946cd7010 Update the file headers across all of the LLVM projects in the monorepo 
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636
 2019-01-19 08:50:56 +00:00
Tom Stellard
a894043910 Revert "AMDGPU/GlobalISel: Implement select for G_INSERT" 
This reverts commit r344310.

The test case was failing on some bots.

llvm-svn: 344317
 2018-10-11 23:36:46 +00:00
Tom Stellard
4733be6e7b AMDGPU/GlobalISel: Implement select for G_INSERT 
Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D53116

llvm-svn: 344310
 2018-10-11 22:49:54 +00:00
Tom Stellard
7c65078f04 AMDGPU/GlobalISel: Add support for G_INTTOPTR 
Summary: This is a no-op.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D52916

llvm-svn: 343839
 2018-10-05 04:34:09 +00:00
Matt Arsenault
0da6350dc8 AMDGPU: Remove remnants of old address space mapping 
llvm-svn: 341165
 2018-08-31 05:49:54 +00:00
Tom Stellard
ac68471326 AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minnun and @llvm.maxnum 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D46172

llvm-svn: 337056
 2018-07-13 22:16:03 +00:00
Tom Stellard
390a5f4774 AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.exp 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45882

llvm-svn: 337046
 2018-07-13 21:05:14 +00:00
Tom Stellard
5bfbae5cb1 AMDGPU: Refactor Subtarget classes 
Summary:
This is a follow-up to r335942.
- Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget
- Rename AMDGPUCommonSubtarget to AMDGPUSubtarget
- Merge R600Subtarget::Generation and GCNSubtarget::Generation into
  AMDGPUSubtarget::Generation.

Reviewers: arsenm, jvesely

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D49037

llvm-svn: 336851
 2018-07-11 20:59:01 +00:00
Matt Arsenault
b1cc4f52ff AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr 
Note a normal select test is not currently possible because this
relies on input registers tracked in SIMachineFunctionInfo which
are not currently serializable in MIR, but this does work end-to-end
from the IR.

llvm-svn: 335490
 2018-06-25 16:17:48 +00:00
Tom Stellard
6af7307650 AMDGPU/GlobalISel: Default to using TableGen'd instruction selector 
Summary:
We can select all instructions that are marked as legal in a full piglit run,
so now is a good time to make the TableGen'd instruction selector default
for all opcodes.  This is NFC for a full piglit run, which is why there are
no tests.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D48198

llvm-svn: 335319
 2018-06-22 03:04:35 +00:00
Tom Stellard
26fac0f8e1 AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D48196

llvm-svn: 335318
 2018-06-22 02:54:57 +00:00
Tom Stellard
9a6535718e AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP 
Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D48195

llvm-svn: 335316
 2018-06-22 02:34:29 +00:00
Tom Stellard
7712ee8891 AMDGPU/GlobalISel: Implement select() for COPY 
Reviewers: arsenm, nhaehnle

Reviewed By: nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46151

llvm-svn: 335315
 2018-06-22 00:44:29 +00:00
Tom Stellard
3f1c6fe156 AMDGPU/GlobalISel: Implement select() for G_IMPLICIT_DEF 
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46150

llvm-svn: 335307
 2018-06-21 23:38:20 +00:00
Tom Stellard
a92847359a AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz 
Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45907

llvm-svn: 334757
 2018-06-14 19:26:37 +00:00
Tom Stellard
46bbbc33c0 AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL 
Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46171

llvm-svn: 334665
 2018-06-13 22:30:47 +00:00