3157 Commits

Author SHA1 Message Date
David Green
4ac2721e51
[AArch64] Add costs for ST3 and ST4 instructions, modelled as store(shuffle). (#87934)
This tries to add some costs for the shuffle in a ST3/ST4 instruction,
which are represented in LLVM IR as store(interleaving shuffle). In
order to detect the store, it needs to add a CxtI context instruction to
check the users of the shuffle. LD3 and LD4 are added, LD2 should be a
zip1 shuffle, which will be added in another patch.

It should help fix some of the regressions from #87510.
2024-04-09 16:36:08 +01:00
Simon Pilgrim
78f0871bee Revert rG58de1e2c5eee548a9b365e3b1554d87317072ad9 "Fix stack layout for frames larger than 2gb (#84114)"
This is failing on some EXPENSIVE_CHECKS buildbots
2024-03-27 16:16:15 +00:00
Wesley Wiser
58de1e2c5e
Fix stack layout for frames larger than 2gb (#84114)
For very large stack frames, the offset from the stack pointer to a local can be more than 2^31 which overflows various `int` offsets in the frame lowering code.

This patch updates the frame lowering code to calculate the offsets as 64-bit values and resolves the overflows, resulting in the correct codegen for very large frames.

Fixes #48911
2024-03-27 15:05:58 +00:00
Sergei Barannikov
5e5b656102
[MC] Make MCParsedAsmOperand::getReg() return MCRegister (#86444) 2024-03-25 05:13:48 +03:00
paperchalice
ef57977f2a
[NewPM][Hexagon] Add HexagonPassRegistry.def (#86244)
Prepare for dag-isel, also migrate some test case
2024-03-23 15:02:27 +08:00
quic-areg
31f4b329c8
[Hexagon] ELF attributes for Hexagon (#85359)
Defines a subset of attributes and emits them to a section called
.hexagon.attributes.

The current attributes recorded are the attributes needed by
llvm-objdump to automatically determine target features and eliminate
the need to manually pass features.
2024-03-19 16:22:30 -05:00
Jeremy Morse
b9d83eff25
[NFC][RemoveDIs] Use iterators for insertion at various call-sites (#84736)
These are the last remaining "trivial" changes to passes that use
Instruction pointers for insertion. All of this should be NFC, it's just
changing the spelling of how we identify a position.

In one or two locations, I'm also switching uses of getNextNode etc to
using std::next with iterators. This too should be NFC.

---------

Merged by: Stephen Tozer <stephen.tozer@sony.com>
2024-03-19 16:36:29 +00:00
David Green
601e102bdb
[CodeGen] Use LocationSize for MMO getSize (#84751)
This is part of #70452 that changes the type used for the external
interface of MMO to LocationSize as opposed to uint64_t. This means the
constructors take LocationSize, and convert ~UINT64_C(0) to
LocationSize::beforeOrAfter(). The getSize methods return a
LocationSize.

This allows us to be more precise with unknown sizes, not accidentally
treating them as unsigned values, and in the future should allow us to
add proper scalable vector support but none of that is included in this
patch. It should mostly be an NFC.

Global ISel is still expected to use the underlying LLT as it needs, and
are not expected to see unknown sizes for generic operations. Most of
the changes are hopefully fairly mechanical, adding a lot of getValue()
calls and protecting them with hasValue() where needed.
2024-03-17 18:15:56 +00:00
Philip Reames
bb9ca8afc0 [Hexagon][TTI] Remove two overrides which simply proxy to base class [NFC]
These serve no point, and slightly complicate a refectoring I'm working
on for this API.
2024-03-15 10:19:54 -07:00
Arthur Eubanks
94c988bcfd [NFC] Remove unused parameter from shouldAssumeDSOLocal() 2024-03-11 19:48:17 +00:00
Justin Lebar
fab2bb8bfd
Add llvm::min/max_element and use it in llvm/ and mlir/ directories. (#84678)
For some reason this was missing from STLExtras.
2024-03-10 20:00:13 -07:00
AtariDreams
7c21495fee
Reapply "Convert many LivePhysRegs uses to LiveRegUnits" (#84338)
This only converts the instances where all that is needed is to change
the variable type name.

Basically, anything that involves a function that LiveRegUnits does not
directly have was skipped to play it safe.

Reverts
7a0e222a17
2024-03-08 19:05:00 +05:30
David Green
44be5a7fdc
[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)
This is another part of #70452 which makes getMemOperandsWithOffsetWidth
use a LocationSize for Width, as opposed to the unsigned it currently
uses. The advantages on it's own are not super high if
getMemOperandsWithOffsetWidth usually uses known sizes, but if the
values can come from an MMO it can help be more accurate in case they
are Unknown (and in the future, scalable).
2024-03-06 17:40:13 +00:00
yandalur
f7d354af57
[Hexagon] Fix shift value when folding shl DAG node (#83853)
When folding (or (shl xx, s), (zext y)) to (COMBINE (shl xx, s-32), y),
fix resulting shift value in HexagonISD::COMBINE node to not generate
negative values.

---------

Co-authored-by: Yashas Andaluri <yandalur@qti.qualcomm.com>
2024-03-06 08:17:02 -06:00
Sumanth Gundapaneni
ca9d2e923b
[Hexagon] Add Loop Alignment pass. (#83379)
Inspect a basic block and if its single basic block loop with a small
number of instructions, set the Loop Alignment to 32 bytes. This will
avoid the cache line break in the first packet of loop which will cause
a stall per each execution of loop.
2024-02-29 16:57:33 -06:00
Sumanth Gundapaneni
962f3e4e5b
[Hexagon] Use the correct call to detect debug instructions (#83373) 2024-02-29 09:51:52 -06:00
Sumanth Gundapaneni
f44c3facca
Revert "[Hexagon] Optimize post-increment load and stores in loops. (… (#83151)
…#82418)"

This reverts commit d62ca8def395ac165f253fdde1d93725394a4d53.
2024-02-27 12:50:22 -06:00
Rishabh Bali
fe42e72db2
[CodeGen] Port AtomicExpand to new Pass Manager (#71220)
Port the `atomicexpand` pass to the new Pass Manager. 
Fixes #64559
2024-02-25 18:42:22 +05:30
Sumanth Gundapaneni
aaf2d078b6
[Hexagon] Clean up redundant transfer instructions. (#82663)
This patch adds a Hexagon specific backend pass that cleans up redundant
transfers after register allocation.
2024-02-22 17:31:37 -06:00
yandalur
6599c022be
[HEXAGON] Fix bit boundary for isub_hi in HexagonBitSimplify (#82336)
Use bit boundary of 32 for high subregisters in HexagonBitSimplify. This
fixes the subregister used in an upper half register store.
2024-02-22 11:48:06 -06:00
Sumanth Gundapaneni
d62ca8def3
[Hexagon] Optimize post-increment load and stores in loops. (#82418)
This patch optimizes the post-increment instructions so that we can
packetize them together.
v1 = phi(v0, v3')
v2,v3  = post_load v1, 4
v2',v3'= post_load v3, 4

This can be optimized in two ways

v1 = phi(v0, v3')
v2,v3' = post_load v1, 8
v2' = load v1, 4
2024-02-21 19:50:47 -06:00
Sumanth Gundapaneni
4c0fdcdb33
[Hexagon] Generate absolute-set load/store instructions. (#82034)
The optimization finds the loads/stores of a specific form and translate
the first load/store to an absolute-set form there by optimizing out the
transfer and eliminate the constant extenders.
2024-02-21 19:50:29 -06:00
Sumanth Gundapaneni
1219214a3b
[Hexagon] Update InstrInfo to include LD/ST offsets of vector instructions (#82386)
The hook HexagonInstrInfo::isValidOffset() is updated to evaluate
offsets of missed LD/ST vector instructions.
2024-02-20 15:29:05 -06:00
Krasimir Georgiev
49a8fc0da4 Revert "[Hexagon] Optimize post-increment load and stores in loops. (#82011)"
This reverts commit 0e6a48c3e8cc53f9eb5945ec04f8e03f6d2bae37.

Temporary revert as it causes bad codegen: https://github.com/llvm/llvm-project/pull/82011#issuecomment-1951426107
2024-02-20 12:15:23 +00:00
Sumanth Gundapaneni
0e6a48c3e8
[Hexagon] Optimize post-increment load and stores in loops. (#82011)
This patch optimizes the post-increment instructions so that we can
packetize them together.
v1 = phi(v0, v3')
v2,v3  = post_load v1, 4
v2',v3'= post_load v3, 4

This can be optimized in two ways

v1 = phi(v0, v3')
v2,v3' = post_load v1, 8
v2' = load v1, 4
2024-02-16 16:47:54 -06:00
sgundapa
de16a05af0
[Hexagon] Fix zero extension of bit predicates with vtrunehb (#81772)
vector extension from v4i1 to v4i8 generates an incorrect word. This
patch uses a vtrunehb for truncation to fix the bug.
2024-02-14 13:10:18 -06:00
Ikhlas Ajbar
76e3759d8d
[Hexagon] Order objects on the stack by their alignments (#81280)
This patch sorts stack objects by their alignment value from the largest
to the smallest. If two objects have the same alignment, then they are
sorted by their size from the largest to the smallest. This minimizes
padding and reduces run time stack size.
2024-02-10 14:42:50 -06:00
Abinaya Saravanan
ac0577177f
[HEXAGON] Add basic block limit for RDF optimizations (#81071)
Skip RDF optimizations if a function contains a number of basic blocks
that is more than a limit

---------

Co-authored-by: Yashas Andaluri <quic_yandalur@quicinc.com>
2024-02-08 21:45:15 -06:00
Philip Reames
3ff7caea33
[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339) 2024-02-01 17:52:35 -08:00
Nico Weber
184ca39529
[llvm] Move CodeGenTypes library to its own directory (#79444)
Finally addresses https://reviews.llvm.org/D148769#4311232 :)

No behavior change.
2024-01-25 12:01:31 -05:00
quic-asaravan
dc5b4daae7
[HEXAGON] Inlining Division (#79021)
This patch inlines float division function calls for hexagon.

Co-authored-by: Awanish Pandey <awanpand@codeaurora.org>
2024-01-24 09:30:33 -06:00
Kazu Hirata
24790a7788 [Hexagon] Use llvm::children (NFC) 2024-01-20 18:57:31 -08:00
quic-akaryaki
96542c018f
[Hexagon] Flip subreg bit for reverse pairs hvx .new (#75873)
In .new instructions, the upper vector of a reverse pair (e.g. V4 in
V4:5) should be referenced with an odd sss value.
2024-01-18 15:04:32 -06:00
Kazu Hirata
7528cf5ef2 [Target] Use getConstantOperandVal (NFC) 2024-01-14 00:53:29 -08:00
Nikita Popov
6c2fbc3a68
[IRBuilder] Add CreatePtrAdd() method (NFC) (#77582)
This abstracts over the common pattern of creating a gep with i8 element
type.
2024-01-12 14:21:21 +01:00
Alex Bradbury
197214e39b
[RFC][SelectionDAG] Add and use SDNode::getAsZExtVal() helper (#76710)
This follows on from #76708, allowing
`cast<ConstantSDNode>(N)->getZExtValue()` to be replaced with just
`N->getAsZextVal();`
    
Introduced via `git grep -l "cast<ConstantSDNode>\(.*\).*getZExtValue" |
xargs sed -E -i
's/cast<ConstantSDNode>\((.*)\)->getZExtValue/\1->getAsZExtVal/'` and
then using `git clang-format` on the result.
2024-01-09 12:25:17 +00:00
paperchalice
ffb1f20e0d
[CodeGen] Add flag to populate target pass names (#76328)
`print-pipeline-passes` can show target pass names.
2024-01-03 09:07:02 +08:00
Alex Bradbury
80aeb62211
[llvm][NFC] Use SDValue::getConstantOperandVal(i) where possible (#76708)
This helper function shortens examples like
`cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();` to
`Node->getConstantOperandVal(1);`.

Implemented with:
`git grep -l
"cast<ConstantSDNode>\(.*->getOperand\(.*\)\)->getZExtValue\(\)" | xargs
sed -E -i

's/cast<ConstantSDNode>\((.*)->getOperand\((.*)\)\)->getZExtValue\(\)/\1->getConstantOperandVal(\2)/`
and `git grep -l
"cast<ConstantSDNode>\(.*\.getOperand\(.*\)\)->getZExtValue\(\)" | xargs
sed -E -i

's/cast<ConstantSDNode>\((.*)\.getOperand\((.*)\)\)->getZExtValue\(\)/\1.getConstantOperandVal(\2)/'`.
With a couple of simple manual fixes needed. Result then processed by
`git clang-format`.
2024-01-02 13:14:28 +00:00
Kazu Hirata
af8d050286 [Target] Use range-based for loops (NFC) 2023-12-24 23:09:55 -08:00
Kazu Hirata
1daf2994de [llvm] Use StringRef::contains (NFC) 2023-12-23 22:21:52 -08:00
Paul Walker
dea16ebd26
[LLVM][IR] Replace ConstantInt's specialisation of getType() with getIntegerType(). (#75217)
The specialisation will not be valid when ConstantInt gains native
support for vector types.

This is largely a mechanical change but with extra attention paid to constant
folding, InstCombineVectorOps.cpp, LoopFlatten.cpp and Verifier.cpp to
remove the need to call `getIntegerType()`.

Co-authored-by: Nikita Popov <github@npopov.com>
2023-12-18 11:58:42 +00:00
Kazu Hirata
586ecdf205
[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)
This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
2023-12-11 21:01:36 -08:00
Kazu Hirata
55531e715f [Target] Remove unused forward declarations (NFC) 2023-12-10 10:38:55 -08:00
Kazu Hirata
286ef12b47 [Target] Remove unnecessary includes (NFC) 2023-12-07 21:03:56 -08:00
Craig Topper
e87f33d9ce
[RISCV][MC] Pass MCSubtargetInfo down to shouldForceRelocation and evaluateTargetFixup. (#73721)
Instead of using the STI stored in RISCVAsmBackend, try to get it from
the MCFragment.

This addresses the issue raised here
https://discourse.llvm.org/t/possible-problem-related-to-subtarget-usage/75283
2023-12-07 13:17:58 -08:00
Kazu Hirata
92c2529ccd [llvm] Stop including vector (NFC)
Identified with clangd.
2023-12-03 22:32:21 -08:00
Kazu Hirata
57eb4826e5 [llvm] Stop including string (NFC)
Identified with clangd.
2023-12-03 16:24:43 -08:00
Kazu Hirata
f25daa589e [llvm] Stop including llvm/ADT/StringRef.h (NFC)
Identified with clangd.
2023-12-03 10:34:48 -08:00
Ramkumar Ramachandra
9468de48fc
TargetInstrInfo: make getOperandLatency return optional (NFC) (#73769)
getOperandLatency has the following behavior: it returns -1 as a special
value, negative numbers other than -1 on some target-specific overrides,
or a valid non-negative latency. This behavior can be surprising, as
some callers do arithmetic on these negative values. Change the
interface of getOperandLatency to return a std::optional<unsigned> to
prevent surprises in callers. While at it, change the interface of
getInstrLatency to return unsigned instead of int.

This change was inspired by a refactoring in
TargetSchedModel::computeOperandLatency.
2023-12-01 11:29:19 +00:00
Nikita Popov
7eeedc124f [CodeGen] Make some includes explicit (NFC)
Explicitly include some headers or forward-declare types, in
preparation for removing an include that pulls in many transitive
headers.
2023-11-24 14:43:18 +01:00