This patch defines the `LVZ` and `LBT` extension instructions, which
provide enough definitions for llvm-mc and llvm-objdump to correctly
handle these instructions.
It also defines the `SCR` (Scratchpad Register) register class, which
are used by the `LBT` extension instructions.
Reviewed By: SixWeining, xen0n
Differential Revision: https://reviews.llvm.org/D155917
This patch adds the definition of the LASX instructions, providing
support only for assembly and disassembly, similar to D154183.
Depends on D154183
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D154195
This patch adds the definition for the `LSX` registers and instructions.
It also adds handling for new immediate operands in the AsmParser. This
patch ensures that llvm-mc and llvm-objdump correctly handle the `LSX`
instructions.
We expand those pseudo-instructions `vrepli.{b,h,w,d}` in the
MCCodeEmitter. This increases the readability of the output when
generating assembly files.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D154183
The name `MCFixedLenDisassembler.h` is out of date after D120958.
Rename it as `MCDecoderOps.h` to reflect the change.
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D124987
These instructions are added by following the `LoongArch Reference
Manual Volume 1: Basic Architecture Version 1.00`.
Differential Revision: https://reviews.llvm.org/D123988
All LLVM backends use MCDisassembler as a base class for their
instruction decoders. Use "const MCDisassembler *" for the decoder
instead of "const void *". Remove unnecessary static casts.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D122245
With the addition of disassembler now we can do instructions 'round-trip' test
that assembles `.s` to obj with `llvm-mc` and disassembles it with `llvm-objdump`
to check instruction mnemonics.
Reviewed By: xen0n, MaskRay
Differential Revision: https://reviews.llvm.org/D120477
