12 Commits

Author SHA1 Message Date
wanglei
2cf420d5b8 [LoongArch] Emit function call code sequence as PCADDU18I+JIRL in medium code model
According to the description of the psABI v2.20:
https://github.com/loongson/la-abi-specs/releases/tag/v2.20, adjustments
are made to the function call instructions under the medium code model.

At the same time, AsmParser has already supported parsing the call36 and
tail36 macro instructions.
2024-01-05 10:56:47 +08:00
WANG Xuerui
00786d3a5f [LoongArch] Support CodeModel::Large codegen
This is intended to behave like GCC's `-mcmodel=extreme`.

Technically the true GCC equivalent would be `-mcmodel=large` which is
not yet implemented there, and we probably do not want to take the
"Large" name until things settle in GCC side, but:

* LLVM does not have a `CodeModel::Extreme`, and it seems too early to
  have such a variant added just for enabling LoongArch; and
* `CodeModel::Small` is already being used for GCC `-mcmodel=normal`
  which is already a case of divergent naming.

Regarding the codegen, loads/stores immediately after a PC-relative
large address load (that ends with something like `add.d $addr, $addr,
$tmp`) should get merged with the addition into corresponding `ldx/stx`
ops, but is currently not done. This is because pseudo-instructions are
expanded after instruction selection, and is best fixed with a separate
change.

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D150522
2023-06-21 16:41:10 +08:00
wanglei
506e936871 [LoongArch] Fix wrong VariantKind for MO_GOT_PC_{HI/LO} flags
Differential Revision: https://reviews.llvm.org/D135946
2022-10-15 17:45:08 +08:00
wanglei
d1b526fb95 [LoongArch] Add codegen support of GlobalTLSAddress lowering
There are static and dynamic TLS address lowering in DAG stage according
to different TLS models.

TLS address will be lowered to pseudo instruction and then expanded by
the `LoongArch Pre-RA pseudo instruction expansion` pass.

Differential Revision: https://reviews.llvm.org/D134713
2022-10-11 18:10:13 +08:00
wanglei
75265c7f49 [LoongArch] Lower BlockAddress/JumpTable
This patch uses a unified interface for lower GlobalAddress ConstantPool
BlockAddress and JumpTable.

This patch allows lowering addresses by using PC-relative addressing
for DSO-local symbols, and accessing the address through the global
offset table for DSO-preemptable symbols.

Remove hardcoded `MininumJumpTableEntries` for test lower JumpTable.

Also updated some test cases using ConstantPool, due to the addition of
relocation information.

Differential Revision: https://reviews.llvm.org/D134431
2022-09-26 10:52:54 +08:00
wanglei
bf47954703 [LoongArch] Add more fixups and relocations
This patch makes the assembler support all modifiers defined in gnu-as.
Also changes some diagnostic information.

Differential Revision: https://reviews.llvm.org/D132633
2022-09-05 14:55:18 +08:00
wanglei
c2ee21cf3f [LoongArch] Add some fixups and relocations
This patch only add %pc_hi20/%pc_lo12/%plt relocations in order
to be able to generate gnu ld linkable relocation file for the
`hello world` IR :
```
@.str = private unnamed_addr constant [14 x i8] c"Hello world!\0A\00", align 1

define dso_local signext i32 @main() nounwind {
entry:
  %call = call signext i32 (ptr, ...) @printf(ptr noundef @.str)
  ret i32 0
}

declare dso_local signext i32 @printf(ptr noundef, ...)
```

This patch also updates some test cases due to new modifiers introduced.
New test: test/MC/LoongArch/Relocations/relocations.s

Differential Revision: https://reviews.llvm.org/D132108
2022-08-20 11:19:24 +08:00
gonglingqin
aeaca854d1 [LoongArch] Add codegen support for handling floating point immediates
Differential Revision: https://reviews.llvm.org/D128898
2022-07-07 08:13:33 +08:00
Weining Lu
d29215790f [LoongArch] Add codegen support for division operations
These operations include sdiv/udiv/srem/urem.

As the ISA [https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_div_wudu_mod_wudu]
described, when the divisor is 0, the result can be any value, but no
exception will be triggered. Unlike gcc, which by default emit code
that checks divide-by-zero after the division or modulus instruction,
we only emit this check when the `-loongarch-check-zero-division`
option is passed.

Differential Revision: https://reviews.llvm.org/D128572
2022-07-06 17:54:57 +08:00
wanglei
b940fe6fe2 [LoongArch] Add codegen support for conditional branches
Setting ISD::BR_CC to Expand makes it much easier to deal with
matching the expanded form.

Differential Revision: https://reviews.llvm.org/D128428
2022-07-05 11:59:58 +08:00
wanglei
5b4851ed91 [LoongArch] Add codegen support for load/store operations
This patch also support lowering global addresses.

Differential Revision: https://reviews.llvm.org/D128427
2022-07-05 11:58:20 +08:00
Lu Weining
33388ae866 [LoongArch 4/6] Add basic tablegen infra for LoongArch
This patch introduces basic tablegen infra such as
LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td.

For now, only add instruction definitions for LoongArch basic integer
operations.
Our initial target is a working MC layer rather than codegen,
so appropriate SelectionDAG patterns will come later.

Differential revision: https://reviews.llvm.org/D115861
2022-02-10 10:23:34 +00:00