This is a follow-on to https://reviews.llvm.org/D134073.
After https://reviews.llvm.org/D137653 we can now switch the PPC
target away from positional operand matching.
This patch fixes all of the "easy" cases. While this changes a large
number of lines of tablegen source, it results in only a single
non-comment change in the code generated by tablegen: the (unused)
codegen-only "MTVRSAVEv" instruction was previously incorrectly
encoding operand 0, and now encodes (correctly) operand 1.
Changes which result in generated-code changes have been split off
into the next (smaller) patch, for ease of review.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D137661
Add a new instruction called SUBUFS that does saturating subtract.
This instruction is only for Future CPU.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D137643
A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.
This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.
Reviewed By: amyk, saghir
Differential Revision: https://reviews.llvm.org/D136366
