LEA_ADDri and LEAX_ADDri are printed / encoded the same way as ADDri. I
had to change the type of simm13Op so that it can be used in both 32-
and 64-bit modes. This required the changes in operands of some
InstAliases.
This change allows to simplify SparcAsmParser a bit by delegating some
work (parsing singleton registers) to the code generated by llvm-tblgen.
Other than that, there is no functionality change, because registers are
matched using custom code in SparcAsmParser.cpp and always printed in
lowercase by SparcInstPrinter.
This adds named ASI tag constants (such as #ASI_P and #ASI_P_L) for memory
accesses.
This patch adds 64-bit/V9 tag names, given that currently the majority of SPARC
software targets that arch.
Support for 32-bit/V8 tag names will be added in a future patch.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157235
This extends support for ASI-tagged loads, stores, and swaps with the new
stored-ASI form ([reg+imm] %asi) introduced in v9.
CAS instructions are handled differently by the (dis-)assembler, so it will be
handled in a separate patch.
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157233
This adds definitions for SPARC v9 State Registers (privileged/nonprivileged,
see v9 manual ch. 5).
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D157231
On 64-bit target, when doing i64 BR_CC where one of the comparison operands is a
constant zero, try to fold the compare and BPcc into a BPr instruction.
For all integers, EQ and NE comparison are available, additionally for signed
integers, GT, GE, LT, and LE is also available.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D142461
On 64-bit target, when doing i64 BR_CC where one of the comparison operands is a
constant zero, try to fold the compare and BPcc into a BPr instruction.
For all integers, EQ and NE comparison are available, additionally for signed
integers, GT, GE, LT, and LE is also available.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D142461
Integrate the BranchRelaxation pass to help with relaxing out-of-range
conditional branches.
This is mostly of concern for SPARCv9, which uses conditional branches with
much smaller range than its v8 counterparts.
(Some large autogenerated code, such as the ones generated by TableGen, already
hits this limitation when building in Release)
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D142458
On 64-bit target, when doing i64 SELECT_CC where one of the comparison operands
is a constant zero, try to fold the compare and MOVcc into a MOVr instruction.
For all integers, EQ and NE comparison are available, additionally for signed
integers, GT, GE, LT, and LE is also available.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D138922
* Prevent the generation of invalid shift instructions by constraining
the immediate field. I've limited the shift field to constant values
only, adding the `R_SPARC_5`/`R_SPARC_6` relocations is trivial if
needed (but I can't really think of a use case for those).
* Fix the generation of PC-relative `call`
* Fix the transformation of `jmp sym` into `jmpl`
* Emit fixups for simm13 operands
I moved the choice of the correct relocation into the code emitter as I've
seen the other backends do, it can be definitely cleaner but the aim was
to reduce the scope of the patch as much as possible.
Fixes the problems raised by joerg in L254199
Reviewed By: dcederman
Differential Revision: https://reviews.llvm.org/D78193
printInst prints a branch/call instruction as `b offset` (there are many
variants on various targets) instead of `b address`.
It is a convention to use address instead of offset in most external
symbolizers/disassemblers. This difference makes `llvm-objdump -d`
output unsatisfactory.
Add `uint64_t Address` to printInst(), so that it can pass the argument to
printInstruction(). `raw_ostream &OS` is moved to the last to be
consistent with other print* methods.
The next step is to pass `Address` to printInstruction() (generated by
tablegen from the instruction set description). We can gradually migrate
targets to print addresses instead of offsets.
In any case, downstream projects which don't know `Address` can pass 0 as
the argument.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D72172
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
llvm-svn: 360506
