9 Commits

Author SHA1 Message Date
Harvin Iriawan
db158c7c83 [AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55.
  Main benefits are to the little core, and introducing SVE scheduling information.
  Changes tested on various OoO cores, no performance degradation is seen.

  Differential Revision: https://reviews.llvm.org/D156799
2023-08-21 12:25:15 +01:00
David Green
21df504399 [DAG][ARM][AArch64] Transform max(a,b) - min(a,b) -> abd(a,b)
This adds both signed and unsigned transforms for
max(a, b) - min(a, b) -> abd(a, b).

unsigned: https://alive2.llvm.org/ce/z/RF4jGQ
signed: https://alive2.llvm.org/ce/z/Cjr2zE

Fixes: #59894

Differential Revision: https://reviews.llvm.org/D141706
2023-01-18 11:44:26 +00:00
David Green
e26ec330c4 [DAG][AArch64][ARM] Combine abd(sub(x, y)) to abd if the sub is nsw
This implements the fold (abs (sub nsw x, y)) -> abds(x, y). Providing
the sub is nsw this appears to be valid without the extensions that are
usually used for abds. https://alive2.llvm.org/ce/z/XHVaB3. The
equivalent abdu combine seems to not be valid.

Differential Revision: https://reviews.llvm.org/D141665
2023-01-18 10:10:52 +00:00
David Green
72290a359a [AArch64] Add tests for forming abd from wrap flags and min/max. NFC 2023-01-16 18:55:10 +00:00
Karl Meakin
d29fc6e7d2 [AArch64] Replace performANDSCombine with performFlagSettingCombine.
`performFlagSettingCombine` is a generalised version of `performANDSCombine` which also works on  `ADCS` and `SBCS`.

Differential revision: https://reviews.llvm.org/D124464
2022-05-12 22:17:23 +01:00
Karl Meakin
81904454f7 [AArch64] Add foldOverflowCheck DAG combine
Differential Revision: https://reviews.llvm.org//D123779
2022-04-21 14:56:38 +01:00
Karl Meakin
13403a70e4 [AArch64] Add lowerings for {ADD,SUB}CARRY and S{ADD,SUB}O_CARRY
Differential Revision: https://reviews.llvm.org/D123322
2022-04-21 14:56:37 +01:00
Paul Walker
6457f42bde [DAGCombiner] Extend ISD::ABDS/U combine to handle more cases.
The current ABD combine doesn't quite work for SVE because only a
single scalable vector per scalar integer type is legal (e.g. for
i32, <vscale x 4 x i32> is the only legal scalable vector type).

This patch extends the combine to also trigger for the cases when
operand extension must be retained.

Differential Revision: https://reviews.llvm.org/D115739
2022-02-17 13:32:20 +00:00
Paul Walker
e30525b6a5 [AArch64] Add NEON test cases for ISD::ABDS/U. 2022-01-26 13:05:57 +00:00