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7667 Commits

Author SHA1 Message Date
Chad Rosier
5c8bf9c3db [AArch64] Refactor the NEON scalar reduce pairwise intrinsics, so that they use 
float/double rather than the vector equivalents when appropriate.

llvm-svn: 196833
 2013-12-09 22:47:38 +00:00
Chad Rosier
3b0b3ee71e [AArch64] Refactor NEON scalar reduce pairwise front-end codegen to remove 
unnecessary patterns in tablegen.

llvm-svn: 196832
 2013-12-09 22:47:34 +00:00
Chad Rosier
397ff3945c [AArch64] Remove q and non-q intrinsic definitions in the NEON scalar reduce 
pairwise implementation, using an overloaded definition instead.

llvm-svn: 196831
 2013-12-09 22:47:31 +00:00
Ana Pazos
bde2828ae0 Fix pattern match for movi with 0D result 
Patch by Jiangning Liu.

With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.

llvm-svn: 196806
 2013-12-09 19:29:14 +00:00
Hao Liu
96a587a9f7 [AArch64]Add missing pair intrinsics such as: 
int32_t vminv_s32(int32x2_t a)
which should be compiled into SMINP Vd.2S,Vn.2S,Vm.2S

llvm-svn: 196749
 2013-12-09 03:51:42 +00:00
Hao Liu
868caea6d1 [AArch64]Pattern match failures for truncate store and extend load 
llvm-svn: 196748
 2013-12-09 03:34:08 +00:00
Jiangning Liu
65d8e3422a For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64. 
llvm-svn: 196456
 2013-12-05 02:12:01 +00:00
Kevin Qin
afd095de8b [AArch64 Neon] Add ACLE intrinsic vceqz_f64. 
llvm-svn: 196362
 2013-12-04 08:02:34 +00:00
Kevin Qin
f9832e8de7 [AArch64 NEON] Add missing compare intrinsics. 
llvm-svn: 196360
 2013-12-04 07:53:28 +00:00
Hao Liu
dca64f4a20 [AArch64]Add missing floating point convert, round and misc intrinsics. 
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn

llvm-svn: 196210
 2013-12-03 06:06:55 +00:00
Hao Liu
c250cbc095 AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions. 
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.

llvm-svn: 196208
 2013-12-03 05:58:30 +00:00
Hao Liu
21a461353a AArch64: Add missing scalar pair intrinsics. 
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".

llvm-svn: 196198
 2013-12-03 03:39:47 +00:00
Jiangning Liu
3a541d46a1 Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends. 
llvm-svn: 196192
 2013-12-03 01:33:52 +00:00
Jiangning Liu
94a7bb2130 Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends. 
llvm-svn: 196190
 2013-12-03 01:29:32 +00:00
Chad Rosier
3106de3f9d [AArch64] Implemented vcopy_lane patterns using scalar DUP instruction. 
Patch by Ana Pazos!

llvm-svn: 196151
 2013-12-02 21:05:16 +00:00
Hao Liu
ba38eee8ac AArch64: The pattern match should check the range of the immediate value. 
Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16].

llvm-svn: 195941
 2013-11-29 02:11:22 +00:00
Jiangning Liu
f7b4c7c2ce Add missing test case for bsl_f64 support of AArch64 NEON. 
llvm-svn: 195939
 2013-11-29 01:38:08 +00:00
Jiangning Liu
97aa8cf8b7 Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics. 
llvm-svn: 195843
 2013-11-27 14:02:25 +00:00
Chad Rosier
75290c6307 [AArch64] Add support for NEON scalar floating-point absolute difference. 
llvm-svn: 195803
 2013-11-27 01:45:58 +00:00
Chad Rosier
9653d5c989 [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

llvm-svn: 195788
 2013-11-26 22:17:37 +00:00
Kevin Qin
599c47d0de Refactored the implementation of AArch64 NEON instruction ZIP, UZP 
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().

llvm-svn: 195716
 2013-11-26 03:26:47 +00:00
Kevin Qin
33ca18fdcf [AArch64]Implement 128 bit register copy with NEON. 
llvm-svn: 195713
 2013-11-26 02:33:42 +00:00
Hao Liu
25aed9bb5b Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types. 
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. 
     "%tmp = bitcast i64 %in to <2 x i32>" can't be selected.

llvm-svn: 195424
 2013-11-22 08:47:22 +00:00
Jiangning Liu
a91633a435 For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG. 
llvm-svn: 195408
 2013-11-22 02:45:13 +00:00
Ana Pazos
9ac2fc85d2 Implemented Neon scalar vdup_lane intrinsics. 
Fixed scalar dup alias and added test case.

llvm-svn: 195330
 2013-11-21 08:16:15 +00:00
Ana Pazos
fbc1adbaa7 Implemented Neon scalar by element intrinsics. 
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.

llvm-svn: 195327
 2013-11-21 07:37:04 +00:00
Hao Liu
16edc4675c Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
llvm-svn: 195078
 2013-11-19 02:17:05 +00:00
Jiangning Liu
0c0c1e8598 Implement AArch64 SISD intrinsics for vget_high and vget_low. 
llvm-svn: 195074
 2013-11-19 01:46:48 +00:00
Jiangning Liu
e329114ae5 Add predicate for AArch64 crypto instructions. 
llvm-svn: 195071
 2013-11-19 01:38:31 +00:00
Hao Liu
5a4e4e107d Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors. 
The functions are like: vst1_s8_x2 ...

llvm-svn: 194990
 2013-11-18 06:31:53 +00:00
Ana Pazos
d035209bd7 Implemented aarch64 Neon scalar vmulx_lane intrinsics 
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.

llvm-svn: 194888
 2013-11-15 23:32:10 +00:00
Chad Rosier
0c57c3402e [AArch64] Fix the scalar NEON ACLE functions so that they return float/double 
rather than the vector equivalent.

llvm-svn: 194853
 2013-11-15 21:28:10 +00:00
Kevin Qin
6e0547dfc9 Add test case for AArch64 NEON instruction set misc. 
llvm-svn: 194673
 2013-11-14 06:45:17 +00:00
Kevin Qin
aec95baf1a Implement aarch64 neon instruction class SIMD misc. 
llvm-svn: 194656
 2013-11-14 02:44:13 +00:00
Jiangning Liu
bb60ccf355 Implement AArch64 NEON instruction set AdvSIMD (table). 
llvm-svn: 194648
 2013-11-14 01:57:32 +00:00
Chad Rosier
d3ae5f895e [AArch64] Add support for legacy AArch32 NEON scalar shift by immediate 
instructions.  This patch does not include the shift right and accumulate
instructions.  A number of non-overloaded intrinsics have been remove in favor
of their overloaded counterparts.

llvm-svn: 194598
 2013-11-13 20:05:37 +00:00
Chad Rosier
d3684a0566 [AArch64] The shift right/left and insert immediate builtins expect 3 
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194406
 2013-11-11 19:11:11 +00:00
Chad Rosier
35575e737c [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
llvm-svn: 194394
 2013-11-11 18:04:07 +00:00
Jiangning Liu
f4226f1d7b Implement AArch64 Neon instruction set Perm. 
llvm-svn: 194123
 2013-11-06 03:35:27 +00:00
Jiangning Liu
a50e22ca4f Implement AArch64 Neon instruction set Bitwise Extract. 
llvm-svn: 194118
 2013-11-06 02:25:49 +00:00
Jiangning Liu
d7c52676f6 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. 
llvm-svn: 194085
 2013-11-05 17:42:05 +00:00
Hao Liu
d6b40b51c7 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
 2013-11-05 03:39:32 +00:00
Kevin Qin
97f6aaa8ad Implemented aarch64 neon intrinsic vcopy_lane with float type. 
llvm-svn: 194041
 2013-11-05 02:03:59 +00:00
Tim Northover
ace0bd4d33 AArch64: use default asm operand printing when modifier inapplicable 
If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate
or register) and an operand modifier (E.g. "w" for "print register as wN") then
we need to decide behaviour when the modifier doesn't apply to the constraint.

Previousely produced some combination of an assertion failure and a fatal
error. GCC's behaviour appears to be to ignore the modifier and print the
operand in the default way. This patch should implement that.

llvm-svn: 194024
 2013-11-04 23:04:07 +00:00
Chad Rosier
74b65cd811 [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
llvm-svn: 193816
 2013-10-31 22:36:59 +00:00
Chad Rosier
20e1f20d69 [AArch64] Add support for NEON scalar shift immediate instructions. 
llvm-svn: 193790
 2013-10-31 19:28:44 +00:00
Amara Emerson
f80f95fcc7 [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739
 2013-10-31 09:32:11 +00:00
Chad Rosier
be020d0309 [AArch64] Add support for NEON scalar floating-point compare instructions. 
llvm-svn: 193691
 2013-10-30 15:19:37 +00:00
Weiming Zhao
acf48d75e5 add test cases for frameaddr and returnaddr for aarch64 
llvm-svn: 193626
 2013-10-29 17:01:29 +00:00
Tim Northover
d29ddf6713 AArch64: add 'a' inline asm operand modifier 
This is used in the Linux kernel, and effectively just means "print an
address".

llvm-svn: 193593
 2013-10-29 08:22:33 +00:00