7296 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
558ea41159
[AMDGPU] Reapply 'Sign extend simm16 in setreg intrinsic' (#78492)
We currently force users to use a negative contant in the intrinsic
call. Changing it zext would break existing programs, so just sign
extend an argument.
2024-01-17 17:23:46 -08:00
Mariusz Sikora
c99da46fc1
[AMDGPU][GFX12] Add Atomic cond_sub_u32 (#76224)
Co-authored-by: Vang Thao <Vang.Thao@amd.com>
2024-01-17 19:23:42 +01:00
Petar Avramovic
90bdf76fdb
Revert "AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis" (#78468)
Reverts llvm/llvm-project#76145
2024-01-17 17:41:19 +01:00
Jay Foad
e4c8c58517
[AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on GFX12 (#77929) 2024-01-17 15:57:36 +00:00
Matt Arsenault
af4f1766ae
AMDGPU: Allocate special SGPRs before user SGPR arguments (#78234) 2024-01-17 21:41:50 +07:00
Jay Foad
f12059eb3f
[AMDGPU] Fix llvm.amdgcn.s.wait.event.export.ready for GFX12 (#78191)
The meaning of bit 0 of the immediate operand of S_WAIT_EVENT has been
flipped from GFX11.
2024-01-17 11:59:15 +00:00
Jay Foad
e9e9d1b0b1
[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX12 (#77927) 2024-01-17 11:52:19 +00:00
Petar Avramovic
1fbf533286
AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#76145)
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.

TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.

patch 3 from: https://github.com/llvm/llvm-project/pull/73337
2024-01-17 12:10:24 +01:00
Jay Foad
4a77414660
[AMDGPU] CodeGen for GFX12 8/16-bit SMEM loads (#77633) 2024-01-17 10:28:03 +00:00
Jay Foad
42b9ea841e
[AMDGPU] Increase max scratch allocation for GFX12 (#77625) 2024-01-17 10:25:28 +00:00
Jay Foad
36ef291d63
[AMDGPU] Fix hang caused by VS_CNT handling at calls (#78318)
Fix a potential hang introduced by #77439 and #77935. This line:

  setScoreUB(VS_CNT, getScoreLB(VS_CNT) + getWaitCountMax(VS_CNT));

could potentialy set UB lower than it was before, which confused
SIInsertWaitcnts's fixed point algorithm.

This was only triggered a STORE instruction with an implicit-def, which
seems odd but apparently happens for some spills.
2024-01-17 10:24:29 +00:00
Matt Arsenault
53a3c738a9 AMDGPU: Remove fixed fixme from a test 2024-01-17 16:52:50 +07:00
Fangrui Song
9e9907f1cf
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
2024-01-16 21:54:58 -08:00
Florian Mayer
f3190c78ec
Revert "[AMDGPU] Sign extend simm16 in setreg intrinsic" (#78372)
Reverts llvm/llvm-project#77997

Broke UBSan bots.
2024-01-16 16:37:48 -08:00
Stanislav Mekhanoshin
371fdbaa57
[AMDGPU] Sign extend simm16 in setreg intrinsic (#77997)
We currently force users to use a negative contant in the intrinsic
call. Changing it zext would break existing programs, so just sign
extend an argument.
2024-01-16 09:17:18 -08:00
Pierre van Houtryve
4b0a76a3d7
[GlobalISel] Fix buildCopyFromRegs for split vectors (#77448)
Fixes #77055
2024-01-16 10:04:20 +01:00
Matt Arsenault
480cc413b7
AMDGPU/GlobalISel: Handle inreg arguments as SGPRs (#78123)
This is the missing GISel part of
54470176afe20b16e6b026ab989591d1d19ad2b7
2024-01-16 15:13:31 +07:00
Shilei Tian
d63c2e52e6
[AMDGPU][MC] Remove incorrect _e32 suffix from v_dot2c_f32_f16 and v_dot4c_i32_i8 (#77993)
The two VOP2 instructions cannot be encoded as VOP3.

Fix #54691.
2024-01-15 23:11:50 -05:00
Jay Foad
ba131b7017
[AMDGPU] Do not generate s_set_inst_prefetch_distance for GFX12 (#78190)
GFX12 can still encode the s_set_inst_prefetch_distance instruction but
it has no effect.
2024-01-15 18:20:45 +00:00
Jay Foad
ed60cb8fb9
[AMDGPU] Disable hasVALUPartialForwardingHazard for GFX12 (#78188) 2024-01-15 18:20:10 +00:00
Jay Foad
85705bbf1d
[AMDGPU] Disable hasVALUMaskWriteHazard for GFX12 (#78187) 2024-01-15 18:19:32 +00:00
chuongg3
fcfe1b6482
[GlobalISel] Refactor extractParts() (#75223)
Moved extractParts() and extractVectorParts() from LegalizerHelper
to Utils to be able to use it in different passes.

extractParts() will also try to use unmerge when doing irregular
splits where possible, falling back to extract elements when not.
2024-01-15 16:40:39 +00:00
Jay Foad
f3d07881c8
[AMDGPU] Remove functions with incompatible gws attribute (#78143)
This change is to remove incompatible gws related functions
in order to make device-libs work correctly under -O0 for
gfx1200+

Co-authored-by: Changpeng Fang <changpeng.fang@amd.com>
2024-01-15 16:23:39 +00:00
Krzysztof Drewniak
88871784fd
[AMDGPU] Allow buffer intrinsics to be marked volatile at the IR level (#77847)
In order to ensure the correctness of ptr addrspace(7) lowering, we need
a backwards-compatible way to flag buffer intrinsics as volatile that
can't be dropped (unlike metadata).

To acheive this in a backwards-compatible way, we use bit 31 of the
auxilliary immediates of buffer intrinsics as the volatile flag. When
this bit is set, the MachineMemOperand for said intrinsic is marked
volatile. Existing code will ensure that this results in the appropriate
use of flags like glc and dlc.

This commit also harmorizes the handling of the auxilliary immediate for
atomic intrinsics, which new go through extract_cpol like loads and
stores, which masks off the volatile bit.
2024-01-12 11:20:01 -06:00
Jay Foad
dec74a8347
[AMDGPU] Fix VS_CNT overflow assertion (#77935)
Always set the upper bound for VS_CNT higher than the lower bound.
Before #77439 this code was only executed on function entry where the
lower bound was 0 so it was not a problem.

Fixes #77931
2024-01-12 17:11:19 +00:00
Carl Ritson
6752f1517d
[TwoAddressInstruction] Recompute live intervals for partial defs (#74431)
Force live interval recomputation for a register if its definition is
narrowed to become partial. The live interval repair process cannot
otherwise detect these changes.
2024-01-12 13:26:01 +09:00
Mirko Brkušanin
3867e6689e
[AMDGPU] Add new GFX12 image atomic float instructions (#76946) 2024-01-11 17:28:04 +01:00
Jay Foad
b120dae9bb
[AMDGPU] Support GFX12 VDSDIR instructions WAITVMSRC operand in GCNHazardRecognizer (#77628)
Modify GCNHazardRecognizer::fixLdsDirectVMEMHazard() so the waitvsrc
operand
in gfx12 DS_PARAM_LOAD or DS_DIRECT_LOAD instructions is set
appropriately
depending on whether a hazard is found or not, rather than inserting an
S_WAITCNT_DEPCTR instruction if a hazard needs to be mitigated.

Co-authored-by: Stephen Thomas <Stephen.Thomas@amd.com>
2024-01-11 13:20:19 +00:00
Amara Emerson
bbbe8ecc17
[GlobalISel][Localizer] Allow localization of a small number of repeated phi uses. (#77566)
We previously had a heuristic that if a value V was used multiple times
in a single PHI, then to avoid potentially rematerializing into many predecessors
we bail out. The phi uses only counted as a single use in the shouldLocalize() hook
because it counted the PHI as a single instruction use, not factoring in it may
have many incoming edges.

It turns out this heuristic is slightly too pessimistic, and allowing a small number
of these uses to be localized can improve code size due to shortening live ranges,
especially if those ranges span a call.

This change results in some improvements in size on CTMark -Os:
```
Program                                       size.__text
                                              before         after           diff
kimwitu++/kc                                  451676.00      451860.00       0.0%
mafft/pairlocalalign                          241460.00      241540.00       0.0%
tramp3d-v4/tramp3d-v4                         389216.00      389208.00      -0.0%
7zip/7zip-benchmark                           587528.00      587464.00      -0.0%
Bullet/bullet                                 457424.00      457348.00      -0.0%
consumer-typeset/consumer-typeset             405472.00      405376.00      -0.0%
SPASS/SPASS                                   410288.00      410120.00      -0.0%
lencod/lencod                                 426396.00      426108.00      -0.1%
ClamAV/clamscan                               380108.00      379756.00      -0.1%
sqlite3/sqlite3                               283664.00      283372.00      -0.1%
                           Geomean difference                               -0.0%
```
I experimented with different variations and thresholds. Using 3 instead
of 2 resulted in a further 0.1% improvement on ClamAV but also regressed
sqlite3 by the same %.
2024-01-11 18:57:37 +08:00
Diana Picus
16945bc16d
[AMDGPU] Don't send DEALLOC_VGPRs after calls (#77439)
Calls do not have to wait for VsCnt, so after they return there might
still be scratch stores in progress. It's important that we don't send
the DEALLOC_VGPR message in that case, since that might release the
VGPRs and scratch allocation before those stores are complete.
2024-01-11 09:14:52 +01:00
Jay Foad
08da7ac80c
[AMDGPU] Fix broken sign-extended subword buffer load combine (#77470) 2024-01-10 10:50:13 +00:00
Ivan Kosarev
084f1c2ee0
[AMDGPU][True16] Support V_CEIL_F16. (#73108)
As not all fake instructions have their real counterparts implemented
yet, we specify no AssemblerPredicate for UseFakeTrue16Insts to allow
both fake and real True16 instructions in assembler and disassembler
tests in the -mattr=+real-true16 mode during the transition period.

Source DPP and desitnation VOPDstOperand_t16 operands are still not
supported and will be addressed separately.
2024-01-10 08:46:19 +00:00
Shilei Tian
b629b8662c
[AMDGPU][MC] Use normal ELF syntax for section switching (#77267)
For some reasons `SunStyleELFSectionSwitchSyntax` is set to `true` for
AMDGPU, but according to
https://github.com/llvm/llvm-project/issues/64862#issuecomment-1880419239
that syntax is only limited to Sun system.

Fix #64862.
2024-01-09 14:13:42 -05:00
Matt Arsenault
888a20c466
AMDGPU: Drop amdgpu-no-lds-kernel-id attribute in LDS lowering (#71481)
This is in preparation for moving the run of AMDGPUAttributor earlier.
Currently it infers the lack of the corresponding intrinsic calls,
so if we introduce new ones we need to remove the attribute from any
possible transitive callers. This is more conservative than necessary,
we could try to identify specific subgraphs where LDS globals are not
used.

Other options include teaching the attributor to avoid adding it in
cases
where the lowering may choose the table, but this seems more complex.
Alternatively could add a second run which doesn't seem worth it.

Depends #71349
2024-01-10 00:12:40 +07:00
Saiyedul Islam
4f7c402d9f
[AMDGPU][NFC] Update left over tests for COV5 (#76984)
Update AMDGPU CodeGen lit tests to check for COV5 ABI.
2024-01-09 17:31:42 +05:30
Matt Arsenault
9be29ad48c AMDGPU: Regenerate test checks
Fix test failures after auto-merge of f9fec402896a90f3b09cea359c330f65a0908649
2024-01-09 17:56:27 +07:00
Matt Arsenault
daecc303bb
AMDGPU: Replace sqrt OpenCL libcalls with llvm.sqrt (#74197)
The library implementation is just a wrapper around a call to the
intrinsic, but loses metadata. Swap out the call site to the intrinsic
so that the lowering can see the !fpmath metadata and fast math flags.

Since d56e0d07cc5ee8e334fd1ad403eef0b1a771384f, clang started placing
!fpmath on OpenCL library sqrt calls. Also don't bother emitting
native_sqrt anymore, it's just another wrapper around llvm.sqrt.
2024-01-09 15:13:58 +07:00
Nick Anderson
f1ec0d12bb
Port CodeGenPrepare to new pass manager (and BasicBlockSectionsProfil… (#77182)
Port CodeGenPrepare to new pass manager and dependency
BasicBlockSectionsProfileReader
Fixes: #75380

Co-authored-by: Krishna-13-cyber <84722531+Krishna-13-cyber@users.noreply.github.com>
2024-01-09 13:32:59 +07:00
Jay Foad
daa4728dee
[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825) 2024-01-08 19:13:38 +00:00
Mirko Brkušanin
7ca4473dd9
[AMDGPU] Add new cache flushing instructions for GFX12 (#76944)
Co-authored-by: Diana Picus <Diana-Magda.Picus@amd.com>
2024-01-08 14:06:58 +00:00
Matt Arsenault
bdbaf6e61b
AMDGPU: Make v8bf16/v16bf16 legal types (#76678)
Depends #76217
2024-01-08 18:59:01 +07:00
Simon Pilgrim
7648371c25 Revert 4d7c5ad58467502fcbc433591edff40d8a4d697d "[NewPM] Update CodeGenPreparePass reference in CodeGenPassBuilder (#77054)"
Revert e0c554ad87d18dcbfcb9b6485d0da800ae1338d1 "Port CodeGenPrepare to new pass manager (and BasicBlockSectionsProfil… (#75380)"

Revert #75380 and #77054 as they were breaking EXPENSIVE_CHECKS buildbots: https://lab.llvm.org/buildbot/#/builders/104
2024-01-05 12:28:10 +00:00
Jay Foad
e96e7a9a86
[AMDGPU] Implement readcyclecounter for GFX12 (#76965) 2024-01-05 08:20:52 +00:00
Nick Anderson
e0c554ad87
Port CodeGenPrepare to new pass manager (and BasicBlockSectionsProfil… (#75380)
Port CodeGenPrepare to new pass manager and dependency
BasicBlockSectionsProfileReader
Fixes: #64560

Co-authored-by: Krishna-13-cyber <84722531+Krishna-13-cyber@users.noreply.github.com>
2024-01-05 13:47:56 +07:00
Matt Arsenault
597086c609
DAG: Implement promotion for strict_fp_round (#74332)
Needs an AMDGPU hack to get the selection to work. The ordinary
variant is custom lowered through an almost equivalent target node
that would need a strict variant for additional known bits
optimizations.
2024-01-05 08:44:19 +07:00
Matt Arsenault
47685633a7
AMDGPU: Make v4bf16 a legal type (#76217)
Gets a few code quality improvements. A few cases are worse
from losing load narrowing.
Depends #76213 #76214 #76215
2024-01-05 08:35:07 +07:00
Matt Arsenault
460ffcddd9
AMDGPU: Make bf16/v2bf16 legal types (#76215)
There are some intrinsics are using i16 vectors in place of bfloat
vectors.
Move towards making bf16 vectors legal so these can migrate. Leave the
larger vectors for a later change.

Depends #76213 #76214
2024-01-04 22:31:18 +07:00
Chaitanya
9803de0e8e
[AMDGPU] Add dynamic LDS size implicit kernel argument to CO-v5 (#65273)
"hidden_dynamic_lds_size" argument will be added in the reserved section
at offset 120 of the implicit argument layout.
Add "isDynamicLDSUsed" flag to AMDGPUMachineFunction to identify if a
function uses dynamic LDS.

hidden argument will be added in below cases:

- LDS global is used in the kernel.
- Kernel calls a function which uses LDS global.
- LDS pointer is passed as argument to kernel itself.
2024-01-04 19:05:12 +05:30
Jay Foad
26ff659c39 [AMDGPU] Remove some unused check prefixes 2024-01-04 13:16:46 +00:00
sstipanovic
b4ac4d2264
[NFC][AMDGPU] Move image-atomic-attributes test to test/Assembler. (#76917) 2024-01-04 10:38:18 +01:00