Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen
pipeline. This test prematurely stops at the first one, which doesn't
cleanup the virtual register map and cause an assertion failure. Ideally
we can solve this by teaching `-stop-after` how to stop at the last
instance of a Pass, but we're just marking XFAIL for these two targets
for now.
Some tests failed for NVPTX target, but it seems that NVPTX will be
fixed and the tests will pass. So, just mark the tests as XFAIL
Differential Revision: https://reviews.llvm.org/D124125
