There are many information that can be used for tuning, like
alignments, cache line size, etc. But we can't make all of them
`SubtargetFeature` because some of them are not with enumerable
value, for example, `PrefetchDistance` used by `LoopDataPrefetch`.
In this patch, a searchable table `RISCVTuneInfoTable` is added,
in which each entry contains the CPU name and all tune information
defined in `RISCVTuneInfo`. Each field of `RISCVTuneInfo` should
have a default value and processor definitions can override the
default value via `let` statements.
We don't need to define a `RISCVTuneInfo` for each processor and
it will use the default value (which is for `generic`) if no
`RISCVTuneInfo` defined.
For processors in the same series, a subclass can inherit from
`RISCVTuneInfo` and override the fields. And we can also override
the fields in processor definitions if there are some differences
in the same processor series.
When initilizing `RISCVSubtarget`, we will use `TuneCPU` as the
key to serach the tune info table. So, the behavior here is if
we don't specify the tune CPU, we will use specified `CPU`, which
is expected I think.
This patch almost undoes 61ab106, in which I added tune features
of preferred function/loop alignments. More tune information can
be added in the future.
D144048 has added preferred function and loop alignment to
RISCVSubtarget, but now we need to set them manually for
different processors.
Tune features that set preferred function/loop align to
[2, 64] bytes (align 1 is not here since the min align is 2)
are added. These features can be used in processor
definitions.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D157832
For the "C" Standard Extension/Zca, D45560 enabled 2-byte alignment for
assembly output (e.g. `clang -S a.c`) and D102052 enabled 2-byte alignment for
assembly input and object file output (e.g. `clang -c a.s`).
This patch ports the behavior for code generation and object file output by
adding RISCVELFTargetObjectFile::getTextSectionAlignment (e.g. `clang -c a.c`).
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D150240
Summary:
According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only
allow 32-bit instruction alignment, but instruction allow to be aligned
to 16-bit boundaries for C-extension.
So we just align to 4 bytes and 2 bytes for C-extension is enough.
Reviewers: asb, apazos
Differential Revision: https://reviews.llvm.org/D45560
Patch by Kito Cheng.
llvm-svn: 329899
