R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).
GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).
Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.
Most of the FP constants supported by FLI are positive. For negative FP
constants X whose positive values is supported by FLI, we can use `(FNEG
(FLI -X))` to materialize X.
Following the version bump in #67964 and the bug fix in #68026 I believe
we're ready to mark Zfa as non-experimental. I'll note the GCC torture
suite passes now with Zfa enabled (though it's more of a litmus test
than anything else).
The logic in `RISCVLoadFPImm::getLoadFPImm` recognises that the only
supported negative value is -1.0, but due to a typo returns `false`
otherwise (entry 0, which is -1.0) rather than returning -1 (indicating
no match found).
There's a miscompile currently for negative numbers (other than -1) that
are the negated form of numbers in the fli lookup table. This adds tests
that capture the issue, with a fix to follow in a separate commit/PR.
D143982 confused ceil and floor. Ceil should use fround instructions with 'rup' and floor should use 'rdn'.
Differential Revision: https://reviews.llvm.org/D146516
Previously, we printed all constants in scientific notation with
6 digits of precision. This is not enough to accurately display
the smallest value, but increasing the precision would be too much
for other values.
This patch prints values with fractional bits using only as many digits as
needed. 1*2^-15 and 1*2^-16 will be printed in scientific notation while
the others are printed without scientific notation. The integer values
are printed with a single 0 after the decimal point.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D145645
There are a couple bugs in the current support for this:
-We do all the parsing in single precision so any value less than or
equal to the minimum fp32 is accepted as the minimum value for f64.
-To support fp16 minimum value, getLoadFP32Imm has a special case, but
that causes a miscompile in CodeGen.
Differential Revision: https://reviews.llvm.org/D145542
The f32 matching code for fli was hacked to allow the f16 minimum value
to match for the fli.h instruction in the assembler. This was done
because the assembler parses the floating point literal for fli.h,
fli.s, and fli.d as a single precision value.
Unfortunately, this function is also used by CodeGen and causes
this value to be miscompiled for f32.
Recommit by preames with commit message, various style cleanups, and unaddressed review comments corrected.
This patch implements experimental codegen support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified.
This change does not include support for FLI (upcoming in a follow up change) or FCVTMOD (not relevant for C/C++).
Differential Revision: https://reviews.llvm.org/D143982
